3D Packaging for Integration of Heterogeneous Systems

Abstract

With several new applications getting developed around wearable technologies for Internet of Things (IoT), there has been a growing need for development of the miniaturized systems. Emerging applications in healthcare, structural monitoring, consumer accessories, etc are fuelling the need for these miniaturized hybrid systems. Such micro-nano systems will be enabled through the development of heterogeneous integration technologies that will allow co-packaging of several chips with different functionalities in a single vertical 3D stack. Therefore, the consumer electronics industry has initiated development of 3D integration of CMOS devices in vertical stacks which are electrically interconnected using thru-silicon-via (TSV) technology. This technology is however not suitable for stacks having a complex combination of GaN-HEMT’s, MEMS, microfluidics, optical devices and CMOS. Moreover, due to the cross-contamination issues, most of these devices are never accepted in the standard silicon CMOS foundries. To address these issues, we have developed innovative processing technologies that would allow 3D packaging by the post fab vertical stacking technique, suitable for the packaging industry. In the First Part of the thesis, we have developed processing technologies for the 3D stacking of the homogenous silicon systems. Using them, we have demonstrated a low temperature process to transfer MOS devices on ultra-thin silicon layers (1.5 μm) from a parent substrate to a foreign substrate or stack. In order to enable this transfer, we have analysed and resolved the associated stress issues. Furthermore, we demonstrate three-layer stacking of the ultra-thin silicon layers with functional MOSFET’s in each layer. We extensively characterize the changes in the device performance, which arise due to the transfer process. In the Second Part of the work, we have demonstrated an approach for stacking the III-nitride-on-Si HEMTs and Si-MOSFETs on to a copper substrate. The developed process flow offers a significant improvement in the device behaviour due to the transfer to a thermally conducting substrate like copper. The functional AlGaN/GaN epi-layer stack from the HEMT-on-silicon wafer is lifted-off and bonded to a copper substrate using novel Cu-In bond. Next, an ultra-thin silicon layer (~1.5 μm) with functional NMOS transistors fabricated in-house, on an SOI wafer are separated from the parent SOI wafer and then stacked over the GaN devices already bonded on the copper substrate, using cost-effective epoxy bonding approach. The devices are characterised to study the improvements in their performance. In the Third Part, we have demonstrated a 3D integration method for miniaturisation of hybrid systems. Using this 3D packaging technique, a fluorescence-sensing platform consisting of (i) a silicon photodetector, (ii) plastic optical filters, (iii) commercial LED and (iv) a glass micro-heater chip is demonstrated. We have resolved several fabrication challenges related to planarization, stacking and interconnection of these divergent chips. The above process flow developed in this work, can be scaled to stack a larger number of layers for achieving more complicated systems with enhanced functionality and applications. Finally, we have demonstrated interconnection methodologies using the nonconventional inkjet printing technique for via filling to enable identical die size stacking.