Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter
Abstract
Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis.
The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter.
Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments.
The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method.
A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.
Collections
Related items
Showing items related by title, author, creator and subject.
-
Reduced Switch Count Multi-Level Inverter Structures With Common Mode Voltage Elimination And DC-Link Capacitor Voltage Balancing For IM Drives
Mondal, Gopal (2010-07-29)Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. Voltage operation above semiconductor device limits, lower common mode voltages, ... -
Studies on Single DC Link Fed Multilevel Inverter Topologies by Cascading Flying Capacitor and Floating Capacitor Fed H-Bridges
Pappu, Roshan Kumar (2018-02-27)Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result ... -
Investigation On Dodecagonal Multilevel Voltage Space Vector Structures By Cascading Flying Capacitor And Floating H-Bridge Cells For Medium Voltage IM Drives
Mathew, Jaison (2017-02-16)In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is ...