Reduced Switch Count MultiLevel Inverter Structures With Common Mode Voltage Elimination And DCLink Capacitor Voltage Balancing For IM Drives
Abstract
Multilevel inverter technology has emerged recently as a very important alternative in the area of highpower mediumvoltage energy control. Voltage operation above semiconductor device limits, lower common mode voltages, near sinusoidal outputs together with small dv/dt’s, are some of the characteristics that have made this power converters popular for industry and modern research. However, the existing solutions suffer from some inherent drawbacks like common mode voltage problem, DClink capacitor voltage fluctuation etc. Cascaded multilevel inverter with openend winding induction motor structure promises significant improvements for high power mediumvoltage applications. This dissertation investigates such cascaded multilevel inverters for openend winding induction motor drive with reduced switch count. Similar to the conventional twolevel inverters, other multilevel inverters with PWM control generate alternating common mode voltage (CMV). The alternating common mode voltage coupled through the parasitic capacitors in the machine and results in excessive bearing current and shaft voltage. The unwanted shaft voltage may cross the limit of insulation breakdown voltage and cause motor failure. This alternating common mode voltage adds to the total leakage current through ground conductor and acts as a source of conducted EMI which can interfere with other electronic equipments around.
As the number of level increase in the inverter, different voltage levels are made available by using DClink capacitor banks, instead of using different isolated power supplies. The intermediatecircuit capacitor voltages which are not directly supplied by the power sources are inherently unstable and require a suitable control method for converter operation, preferably without influence on the load power factor. Apart from normal operation, the sudden fault conditions may occur in the system and it is necessary to implement the control strategy considering this condition also.
A fivelevel inverter topology with cascaded power circuit structure is proposed in this dissertation with the strategy to eliminate the common mode voltage and also to maintain the balance in the DClink capacitor voltages. The proposed scheme is based on a dual fivelevel inverter for openend winding induction motor. The principle achievement of this work is the reduction of power circuit complexity in the fivelevel inverter compared to a previously proposed fivelevel inverter structure for openend winding IM drive with common mode voltage elimination. The reduction in the number of power switching devices is achieved by sharing the two twolevel inverters for both the inverter structures. The resultant inverter structure can produce a ninelevel voltage vector structure with the presence of alternating common mode voltage. The inverter structure is formed by cascading conventional twolevel inverters together with NPC threelevel inverters. Thus it offers modular and simpler power bus structure. As the power circuit is realised by cascading conventional twolevel and NPC threelevel inverters the number of power diodes requirements also reduced compared to the conventional NPC fivelevel inverters. The present proposed structure is implemented for the openend winding induction motor and the power circuit offers more number of switching state redundancies compared to any conventional fivelevel inverter. The inverter structure required half the DClink voltage compared to the DClink voltage required for the conventional fivelevel inverter structure for induction motor drive and this reduces the voltage stress on the individual power devices. The common mode voltage is eliminated by selecting only the switching states which do not generate any common mode voltage in pole voltages hence there will be no common mode voltage at the motor phase also. The technique of using the switching state selection for the common mode voltage elimination, cancels out the requirement of the filter for the same purpose. As the inverter output is achieved without the presence of common mode voltage, the dual inverter can be fed from the common DClink sources, without generating any zero sequence current. Hence the proposed dual fivelevel inverter structure requires only four isolated DC supplies.
The multilevel inverters supplied by single power supply, have inherent unbalance in the DClink capacitor voltages. This unbalance in the DClink capacitor voltages causes lower order harmonics at the inverter output, resulting in torque pulsation and increased voltage stress on the power switching devices. A fivelevel inverter with reduced power circuit complexity is proposed to achieve the dual task of eliminating common mode voltage and DClink capacitor voltage balancing. The method includes the analysis of current through the DClink capacitors, depending on the switching state selections. The conditions to maintain all the four DClink capacitor voltages are analysed. In an ideal condition when there is no fault in the power circuit the balance in the capacitor voltages can be maintained by selecting switching states in consecutive intervals, which have opposite effect on the capacitor voltages. This is called the open loop control of DClink capacitor voltage balancing, since the capacitor voltages are not sensed during the selection of the switching states. The switching states with zero common mode voltages are selected for the purpose of keeping the capacitor voltages in balanced condition during no fault condition. The use of any extra hardware is avoided. The proposed open loop control of DClink capacitor voltage balancing is capable of keeping the DClink capacitor voltages equal in the entire modulation region irrespective of the load powerfactor. The problem with the proposed open loop control strategy is that, it can not take any corrective action if there is any initial unbalance in the capacitor voltages or if any unbalance occurs in the capacitor voltages during operation of the circuit,. To get the corrective action in the capacitor voltages due occurrence of any fault in the circuit, the strategy is further improved and a closed loop control strategy for the DClink capacitor voltages is established. All the possible fault conditions in the four capacitors are identified and the available switching states are effectively used for the corrective action in each fault condition. The strategy is implemented such a way that the voltage balancing can be achieved without affecting the output fundamental voltage.
The proposed fivelevel inverter structure presented in this thesis is based on a previous work, where a fivelevel inverter structure is proposed for the openend winding induction motor. In that previous work 48 switches are used for the realization of the power circuit. It is observed that all the available switching states in this previous work are not used for any of the performance requirement of CMV elimination or DClink voltage balancing. So, in this proposed work, the power circuit is optimized by reducing some of the switches, keeping the performance of the inverter same as the power circuit proposed in the previous work. The fivelevel inverter proposed in this thesis used 36 switches and the number of switching states is also reduced. But, the available switching states are sufficient for the CMV elimination and DClink capacitor voltage balancing.
The advantage of the modular circuit structure of this proposed fivelevel inverter is further investigated and the inverter structure is modified to a sevenlevel inverter structure for the open end winding induction motor. The proposed power circuit of the sevenlevel inverter uses only 48 switches, which is less compared to any sevenlevel inverter structure for the open end winding induction motor with common mode voltage elimination. The power circuit is reduced by sharing four twolevel inverters to both the individual sevenlevel inverters in both the sides of the of the open end winding induction motor. The cascaded structure eliminates the necessity of the power diodes as required by the conventional NPC multilevel inverters. The proposed sevenlevel inverter is capable of producing a thirteenlevel voltage vector hexagonal structure with the presence of common mode voltage. The common mode voltage elimination is achieved by selecting only the switching states with zero common mode voltage from both the inverters and the combined inverter structure produce a sevenlevel voltage vector structure with zero common mode voltage. The switching frequency is also reduced for the sevenlevel inverter compared to the proposed fivelevel inverter. The advantage of this kind of power circuit structure is that the number of power diode requirement is same in both fivelevel and sevenlevel inverters. Since there is no common mode voltage in the output voltages, the dual sevenlevel inverter structure can be implemented with the common DClink voltage sources for both the sides. Six isolated power supplies are sufficient for both the sevenlevel inverters.
The available switching states in this proposed sevenlevel inverter are further analysed to implement the open loop and closed loop capacitor voltage balancing and this allow the power circuit to run with only three isolated DC supplies.
All the proposed work presented in this thesis are initially simulated in SIMULINK toolbox and then implemented in a form of laboratory prototype. A 2.5KW open end winding induction motor is used for the implementation of these proposed works. But all these work general in nature and can be implemented for high power drive applications with proper device ratings.
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