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    Fault-tolerant data driven distributed architecture for future generation avionics

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    Sudhakar, Avva
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    Abstract
    The mission requirements of fighter aircraft have become increasingly complex over the years. In addition to the traditional roles of air combat and air?to?ground bombing, the modern combat environment requires penetrating aircraft to avoid or defeat sophisticated air? and ground?based threats. The next?generation aircraft would be expected to fly missions day and night, in any type of weather, and sustain operations with much less maintenance support than what is required at present. The increased pace of warfare and the complexity of new sensors and systems impose higher processing and communication demands on avionics architectures. The ever?increasing requirements of avionics systems have now outgrown the capabilities of present?day avionics architectures. Several study groups in developed countries-such as Pave Pillar and Pave Pace in the USA-are working toward the development of futuristic avionics architectures. However, being defence?oriented initiatives, the outcomes of these studies are classified, and the information available in open literature is limited and sketchy. The main objective of the present study is to develop a new avionics architecture for next?generation military aircraft. To this end, a detailed study of some well?established avionics architectures has been conducted. A critical examination of existing and conceptual avionics bus architectures for both military and civil aircraft has been carried out to highlight their strengths and limitations. The functional capabilities expected of next?generation avionics subsystems are also analyzed. A new Data?Driven Distributed (D³) architecture is proposed for future avionics systems. The proposed D³ architecture provides redundancy and fault tolerance along with modularity and scalability. Additional processing modules can be attached to individual avionics subsystems to enhance computational capacity when required. The D³ architecture uses the Data?Driven Processing Node (DDPN) concept to avoid unnecessary transmissions on the bus and supports multiple message transmissions to achieve higher communication throughput. The D³ topology employs distributed parallel?processor networks interconnected by dual?redundant high?speed data buses. A new Data?Driven Distributed (D³) Protocol governs the communication on these buses. Interconnected clusters of transputers are proposed for implementing avionics subsystems such as navigation and weapon management. An intra?cluster communication protocol has been developed, and fault?tolerance features are incorporated to enhance the overall reliability of the proposed architecture. Standard transputer modules have been used to study both intra?cluster and inter?cluster communication. System?executive software has been written in Occam. A simulation model for an n?node computer?communication network has been developed using the General Purpose Simulation System (GPSS). Queue statistics of the proposed D³ protocol have been collected from the simulation model and compared with published results of comparable protocols. Scenarios involving data redundancy from 10% to 90% have been simulated, and the performance of the proposed protocol has been studied under different bus loads. Node failures have also been simulated to analyze the performance of the protocol under faulty conditions. The throughput of the proposed D³ protocol compares favourably with those of the SAE?9B Linear Bus and Linear Ring protocols, the Fiber Distributed Data Interface (FDDI) protocol, and the Pave Pillar High?Speed Data Bus protocol.
    URI
    https://etd.iisc.ac.in/handle/2005/9326
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    • Electrical Engineering (EE) [448]

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