• Login
    View Item 
    •   etd@IISc
    • Division of Electrical, Electronics, and Computer Science (EECS)
    • Electrical Engineering (EE)
    • View Item
    •   etd@IISc
    • Division of Electrical, Electronics, and Computer Science (EECS)
    • Electrical Engineering (EE)
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    VLSI architecture for the parallel computation of power system problems.

    Thumbnail
    View/Open
    T02667.pdf (3.479Mb)
    Author
    Pereira, Larry I F
    Metadata
    Show full item record
    Abstract
    The large size and modeling complexities of power system problems have been providing the motivation for the use of fast computers and the search for new algorithms. The present trend of using digital computers for the real-time monitoring and control of power systems has given further impetus to work in this area. Looking at the progress achieved in the last decade in serial power system algorithms, one cannot be very optimistic about significant improvements in them. Hence, this thesis attempts to explore the possibilities of parallel processing for improving the speed of power system computations. This thesis proposes the use of VLSI (Very Large Scale Integration) techniques for the fast solution of power system problems, for either off-line or real-time purposes. Since a number of power system algorithms involve the repeated solution of Linear Systems of Equations (LSE) as a major part of the computations, methods to implement this part in parallel are sought, so as to improve the overall solution speed. Two new architectures have been proposed: one for the computation of the inverse of a diagonally dominant matrix using the Gauss-Jordan algorithm, and the other for matrix-vector multiplication. These architectures can be collectively employed to solve a system of linear equations. While the inverse array requires (4n?1) (4n?1) time steps on n n processing elements, the matrix-vector multiplication requires (n+2) (n+2) time steps on a linear array of n n processing elements. A matrix partitioning strategy and a MIMD (Multiple Instruction, Multiple Data) type of architecture for the implementation of this strategy have also been proposed to achieve a further reduction in computation time. A methodology for assessing the speed enhancement that could be achieved by using the proposed VLSI architectures, as compared with a serial implementation, is also proposed. This is done by considering one of the power system problems—Transient Analysis. The solution algorithm chosen for this analysis is the popular algorithm due to Dommel. This study shows that the solution could be speeded up considerably by the proposed VLSI implementation and provides evidence to justify further exploration in this area.
    URI
    https://etd.iisc.ac.in/handle/2005/8931
    Collections
    • Electrical Engineering (EE) [431]

    etd@IISc is a joint service of SERC & J R D Tata Memorial (JRDTML) Library || Powered by DSpace software || DuraSpace
    Contact Us | Send Feedback | Thesis Templates
    Theme by 
    Atmire NV
     

     

    Browse

    All of etd@IIScCommunities & CollectionsTitlesAuthorsAdvisorsSubjectsBy Thesis Submission DateThis CollectionTitlesAuthorsAdvisorsSubjectsBy Thesis Submission Date

    My Account

    LoginRegister

    etd@IISc is a joint service of SERC & J R D Tata Memorial (JRDTML) Library || Powered by DSpace software || DuraSpace
    Contact Us | Send Feedback | Thesis Templates
    Theme by 
    Atmire NV