Performance enhancement through operator caching in reconfigurable architectures

Abstract

The requirement for computing power has been growing at a faster rate than the growth in compute performance. High-performance designs have increasingly been mapped to expensive Application Specific Integrated Circuit (ASIC) implementations, which require large design time and effort. FPGA-based Reconfigurable Computing Systems are seen as a flexible, high-performance alternative to ASIC or software-based system designs. A large amount of the logic resources in FPGAs is dedicated to routing, and the size of the FPGA required to implement complex designs is huge. Partitioning the design into segments that are configured and executed on the FPGA one after another is feasible due to the sequential nature of computing tasks. However, this leads to multiple reconfigurations of the FPGA, requiring a large amount of time to be spent on configuring the FPGA resources. Design methods that balance reconfiguration overhead with compute performance are needed. An Operator Caching-based approach is proposed to reduce the number of reconfigurations and, hence, the associated overhead. The fact that a set of operations is repeatedly executed many times in most real-life programs can be exploited by retaining the corresponding functional unit configurations on the FPGA hardware. A three-dimensional template placement approach to the resource allocation problem that utilizes operator caching, along with a list-based scheduling algorithm, is proposed. Simulation studies show that the schedules generated by our algorithm considerably improve upon previous ones. The potential of operator caching as a means to improve execution times is demonstrated by the 30% average improvement obtained on several benchmarks. The variation in execution delays with the amount of on-chip memory available for storing intermediate data is studied. The simulation results indicate that techniques that reduce configuration and communication overheads can provide substantial improvements in the performance of Reconfigurable Architectures.