Complexity effective ASIP architectures for network processing and multimedia acceleration

Abstract

Advancements in VLSI technology have significantly improved microprocessor performance over the past decades. However, contemporary general-purpose processors fall short in meeting the demands of emerging application domains, particularly in embedded systems. Application Specific Instruction-set Processors (ASIPs) offer a promising solution, but increasing performance requirements have led to complex architectures that raise development costs and design challenges. This thesis presents an architecture-driven approach to reduce ASIP complexity while maintaining performance. Focusing on application analysis and architectural design space exploration, the study evaluates statically scheduled architectures-specifically in-order superscalar and VLIW models—within two domains: network processing and multimedia acceleration. For network processing, the study analyzes open-source benchmarks using the IMPACT toolset and explores compiler optimizations such as superblock and hyperblock techniques. For multimedia acceleration, the thesis investigates simultaneous multistreaming (SMS) and introduces the concept of virtual resources to reduce code size expansion in VLIW architectures without increasing hardware complexity. Simulation results using the Trimaran infrastructure and HPL-PD instruction set demonstrate the effectiveness of these approaches. The research contributes valuable insights into complexity-effective ASIP design, offering scalable solutions for high-performance embedded systems in networking and multimedia domains.