Modeling the Switching Dynamics of Advanced Power Semiconductor Devices: From Silicon Superjunction to Wide Bandgap Technologies

Abstract

The advancement of power semiconductor devices has significantly transformed modern power conversion systems, enabling notable enhancements in energy efficiency, system miniaturization, and overall performance. Among the emerging technologies, silicon superjunction MOSFETs (Si SJMOS), silicon carbide (SiC) MOSFETs, and gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have gained prominence in applications such as renewable energy systems, electric vehicles, and commercial power supplies. While these devices are commonly available in the 600-650 V range, SiC MOSFETs extend to higher voltage ratings of 1200-1700 V, making them well-suited for high-power applications. In power electronic converters, power semiconductor devices incur switching losses during transitions between their on and off states. Advances in device technology have reduced junction capacitance, resulting in faster switching transients and lower losses. However, these improvements also introduce challenges such as oscillations in gate and power loops, increased electromagnetic interference (EMI), crosstalk, false turn-on events, and heightened device stress due to the amplified influence of circuit parasitics. Therefore, an in-depth understanding of switching dynamics is crucial for optimizing device performance and mitigating these issues. This thesis presents a comprehensive investigation into the switching dynamics of advanced power semiconductor technologies (Si SJMOS, SiC MOSFETs, and GaN HEMTs). The study employs circuit-based simulations and mathematical modeling to estimate critical performance parameters, including switching losses, slew rates of voltage (dv/dt), and current (di/dt), transition times, and voltage overshoots. The study begins with developing a mathematical model to characterize the switching transients of Si SJMOS in combination with SiC Schottky barrier diodes (SBDs), which mitigate reverse recovery losses. The model employs a nonlinear channel current formulation based on the Nth power law, effectively capturing the current characteristics in both the ohmic and saturation regions. Additionally, piecewise nonlinear models are introduced for the gate-drain and drain-source capacitances of Si SJMOS and the reverse-biased capacitance of SiC SBDs. The accuracy of the model is validated using experimental results for three pairs of Si SJMOS and SiC SBD. The investigation then extends to wide bandgap (WBG) devices, focusing on GaN HEMTs and SiC MOSFETs rated at 600-650 V. A detailed model is developed for GaN HEMTs, incorporating nonlinear channel current behavior, junction capacitances, and parasitic effects. Experimental results for 650 V, 33 A GaN HEMT validate the accuracy of the model. To represent the switching transients of 650 V SiC MOSFETs, the existing models originally designed for 1200 V devices are adapted and refined. The model is validated through experimental results for a 650 V, 30 A SiC MOSFET. A comparative analysis is then conducted to evaluate the switching performance of 650 V power semiconductor devices, including Si SJMOS, SiC MOSFETs, and multiple GaN HEMT technologies (e-GaN, GaN GIT, and Cascode GaN). Devices with similar voltage (600-650 V) and current (30 A) ratings are assessed in terms of switching losses, transition times, (dv/dt), (di/dt), and voltage overshoots, offering valuable insights into device selection for single-phase applications. Further, the study explores the impact of packaging on the switching behavior of SiC MOSFETs, particularly in Kelvin-source (TO-247-4) configurations. A detailed model is developed that integrates nonlinear channel current characteristics, capacitance models, and circuit parasitic effects. The model is experimentally validated using a 1.2 kV SiC MOSFET. A comparison between TO-247-3 and TO-247-4 packages is also presented, highlighting the impact of packaging on switching performance. In addition, an improved model is proposed to predict crosstalk dynamics in SiC MOSFETs. The model incorporates a nonlinear channel current formulation, parasitic inductances from both the package and PCB, and parasitic capacitances due to PCB layout. These enhancements improve the prediction of (dv/dt)-induced gate-source voltages and the dynamics of false turnon events. Experimental results for two 1200 V SiC MOSFETs validate the models effectiveness. An optimized negative gate voltage and gate resistance design is also proposed to minimize negative gate-source voltage peaks and mitigate false turn-on. Finally, the thesis investigates partial hard turn-on dynamics of SiC MOSFETs in a half-bridge configuration. The study identifies the minimum load current required for zero-voltage switching and quantifies switching losses associated with partial hard turn-on transitions. The findings reveal that these losses deviate significantly from the traditional (1/2)CV2 loss model. Experimental validation is performed using two 1.2kV SiC MOSFETs with varying current ratings. In conclusion, this thesis significantly advances the modeling of switching transients in Si SJMOS, SiC MOSFETs, and GaN HEMTs. By integrating detailed nonlinear representations of channel current and junction capacitances of power devices, as well as circuit parasitic effects, the proposed models enhance the accuracy of predicting the switching behavior of these advanced power semiconductor devices.