Design and performance studies on bus-based multi microcomputer systems

Abstract

(1) Highlight the key attributes of the design space at the processor memory subsystem level of bus-based multimicro-computer systems; and suggest memory placement as well as bus-allocation procedures, which can result in reduced contention and communication overhead. (2) Develop efficient simulation and analytical models which are used to evaluate the performance measures for the system architecture and quantify the effect of possible improvements