| dc.contributor.advisor | Shiva Prasad, A P | |
| dc.contributor.author | Soumyanath, K | |
| dc.date.accessioned | 2025-09-23T12:07:45Z | |
| dc.date.available | 2025-09-23T12:07:45Z | |
| dc.date.submitted | 1984 | |
| dc.identifier.uri | https://etd.iisc.ac.in/handle/2005/7083 | |
| dc.description.abstract | (1) Highlight the key attributes of the design space at the
processor memory subsystem level of bus-based multimicro-computer systems; and suggest memory placement
as well as bus-allocation procedures, which can result
in reduced contention and communication overhead.
(2) Develop efficient simulation and analytical models
which are used to evaluate the performance measures
for the system architecture and quantify the effect
of possible improvements | |
| dc.language.iso | en_US | |
| dc.relation.ispartofseries | T02182 | |
| dc.rights | I grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation | |
| dc.subject | Multi-micro-computer Systems | |
| dc.subject | Memory Interconnection Schemes | |
| dc.subject | Interprocessor Communication | |
| dc.subject.classification | Research Subject Categories::TECHNOLOGY::Electrical engineering, electronics and photonics::Electronics | |
| dc.title | Design and performance studies on bus-based multi microcomputer systems | |
| dc.type | Thesis | |
| dc.degree.name | MSc Engg | |
| dc.degree.level | Masters | |
| dc.degree.grantor | Indian Institute of Science | |
| dc.degree.discipline | Engineering | |
