Design and Fabrication of P3HT-Field Effect Transistors

Abstract

The increasing demand for advanced sensing applications has highlighted the potential of hybrid systems combining silicon technology with organic field-effect transistors (OFETs). Silicon technology-based devices are highly compatible with existing semiconductor systems, allowing seamless integration into established electronic frameworks. This integration allows silicon-based circuits to work in tandem with OFETs, where the latter can be optimized for sensing applications due to their unique properties. Polymer-FETs can be tailored for sensing purposes by engineering their active layers and interfaces to detect specific environmental, chemical, or biological stimuli. They also offer advantages like solution-processability and low-power operation, making them versatile for a range of sensing applications. In this work, P3HT, a widely studied polymer semiconductor, was employed to establish a framework for silicon-integrable fabrication of OFETs. The relevant charge transport properties of P3HT, along with its compatibility with scalable deposition methods, make it an ideal candidate. This enables the exploration of the interplay between polymer semiconductors and silicon technology. By focusing on the dielectric-semiconductor interface and advanced device architectures, this work aims to provide a foundation for the development of polymer-FET systems that could harness re strengths of both silicon technology and organic semiconductors. This work discusses the effects of annealing and octadecyl phosphonic acid (ODPA) treatment on AlOx dielectric layers and their impact on P3HT thin-film formation. Annealing has been shown to reduce hydroxyl groups (OH), as identified through X-ray Photoelectron Spectroscopy (XPS), and introduce oxygen vacancies, which significantly influence the electronic structure of AlOx. These changes have been further analyzed using photoluminescence (PL) and ultraviolet photoelectron spectroscopy (UPS), revealing how annealing alters the dielectric’s electronic properties. The work function of AlOx varies significantly across different treatments, and this variation correlates with noticeable shifts in the work function of P3HT films deposited on these layers. Such changes directly affect the semiconductor’s electronic behavior and overall device performance. Grazing incidence X-ray diffraction (GIXRD) studies highlight the crystalline arrangement of P3HT, with the treatment of AlOx surfaces using ODPA or annealing significantly impacting the crystallinity and molecular packing. ODPA-treated surfaces exhibit enhanced ordering, suggesting a strong relationship between the dielectric surface preparation and the polymer morphology. This study integrates a wide range of characterization techniques, including XPS, UPS, PL, and GIXRD, to provide a comprehensive analysis of the interplay between dielectric and semiconductor interfaces. These findings contribute to an improved understanding of material properties and optimization for P3HT-FETs discussed. AlOx This lead to exploration of the design, fabrication, and characterization of doped silicon back-gated devices, emphasizing the integration of AlOx as a dielectric and P3HT as the active polymer semiconductor. This work investigates the potential of these devices to address challenges in achieving reliable, high-performance organic field-effect transistors (OFETs). Through a combination of material selection and process optimization, this chapter focuses on evaluating the electrical and structural properties critical to device performance. The study begins with the fabrication process, which includes atomic layer deposition (ALD) of aluminum oxide on doped silicon substrates. The OFETs were fabricated using optical lithography and e-beam evaporation of metal to create source and drain electrodes with a channel length of 40 microns. The patterned device substrates were surface-treated, followed by P3HT deposition. Additionally, device fabrication was executed using electron beam lithography to achieve channel sizes down to 100 nm. Electrical measurements, including current-voltage (I-V) analyses, were conducted to evaluate the operational characteristics of the devices. The results highlight key parameters such as mobility, drain-induced barrier lowering, and hysteresis, demonstrating the influence of the dielectric-semiconductor interface on device performance. The impact of annealing and surface treatments on reducing hysteresis and improving charge transport was also analyzed. This work further examines the role of doped silicon as a back-gate electrode, emphasizing its compatibility with scalable device architectures. Detailed discussions on the optimization of gating mechanisms concluded with the development of a field-confined gating approach. Where the fabrication and challenges of advanced gating architectures in P3HT-based OFETs, specifically bottom-gated and in-plane gated devices have been highlighted. The transition to metal gating posed challenges, including altered dielectric thickness due to the lack of hydroxyl (OH) terminations. This change significantly affected the nucleation process during aluminum oxide (AlOx) deposition via atomic layer deposition (ALD).. Surface passivation and controlled nucleation processes were critical to achieving uniform dielectric layers. Optical lithography was used for overlay of source and drain over the pre-patterned gate. In the case of in-plane gating, reactive ion etching was employed to etch away the surrounding material, effectively burying the gate structure beneath the dielectric layer. These fabrication techniques addressed issues such as precision in photoresist slope contrast, uniform deposition, and the gating mechanism’s performance sensitivity to dielectric scaling and interface quality. This work concluded with the need for silicide-based gating as a scalable approach to address limitations in traditional gating mechanisms for P3HT-based OFETs. Silicide gates offer improved compatibility with advanced fabrication techniques, enabling high-density device integration and enhanced performance. Low pressure chemical vapor deposition (LPCVD) was employed to create polycrystalline silicon (PolySi) and amorphous silicon (a-Si) films on thermal oxide wafers. The deposition process was carefully controlled, with deposition rates influenced by the deposition temperature and the type of silicon being deposited. Higher deposition temperatures favored PolySi formation, while lower temperatures facilitated a-Si deposition. The surface roughness of PolySi and a-Si was analyzed to ensure the films met the stringent requirements for subsequent silicidation and dielectric deposition. Surface roughness impacted the uniformity of silicide formation, a critical factor for device scalability and reliability. Nickel silicide was formed through controlled silicidation processes, where the silicide’s recession into the LPCVD-silicon layer was observed, enabling improved dielectric deposition and enhancing the gating mechanism’s reliability and scalability in device performance. This recess could facilitate more uniform dielectric deposition by providing a smoother surface for atomic layer deposition (ALD) of AlOx. The characterization of the silicides was performed using X-ray diffraction (XRD) to identify phase composition and crystallinity. X-ray photoelectron spectroscopy (XPS) and ultraviolet photoelectron spectroscopy (UPS) provided insights into the electronic properties of the silicide interfaces, highlighting their impact on potential gating efficiency and charge modulation. The work concludes with the potential of silicide-based gating for scalable, high-performance OFET fabrication by using ultra-thin dielectrics to achieve effective electric field templating and uniformity.