Investigations into Extending the Linear Modulation Range of Hybrid Three-Level and Five-Level Inverters for Variable Speed Drive Applications

Abstract

Multilevel inverters (MLIs) are highly sought after for medium to high voltage applications, such as traction drives, fans, blowers, HVDC, and FACTS. These inverters provide numerous benefits over conventional two-level inverters, including reduced voltage stress on power switches, lower dv/dt across load terminals, minimized electromagnetic interference (EMI), and decreased total harmonic distortion (THD) for both current and voltage. Unlike two-level inverters, MLIs generate output voltages with multiple discrete steps, closely approximating an ideal sine wave. This results in improved power quality and a reduced need for large, expensive filters. Additionally, MLIs can operate at lower switching frequencies, which decreases power switch losses and enhances overall efficiency. These features make MLIs superior to two-level inverters in all respects, particularly in medium to high-power AC motor drives. Given their advantages, a variety of MLI topologies have been developed. Common types include Neutral Point Clamped (NPC), Flying Capacitor (FC), and Cascaded H-Bridge (CHB) inverters, each with its own set of benefits and drawbacks. As the number of pole voltage levels increases, NPC inverters require more clamping diodes and face neutral point balancing challenges at higher modulation indices. FC inverters necessitate more floating capacitors with increased voltage levels, which require complex balancing algorithms and increased switching losses. CHB inverters need multiple isolated DC sources, making the system bulky and costly while complicating regeneration operations. To address these limitations, various hybrid MLI configurations have been proposed. This thesis focuses on three-level and five-level inverters, which are the most widely used among MLIs. The primary objective in developing new MLI schemes is to optimize component count and improve reliability. This thesis proposes hybrid three- and five-level MLI schemes utilizing a single DC link with reduced component counts. A single DC link simplifies four-quadrant operation and enhances the reliability of these schemes. In the event of a switch fault within the cascaded H-bridge stages, the proposed schemes can continue to operate at the drive’s rated power. The capacitors in these schemes are charged by the phase current, eliminating the need for additional pre-charging circuits. Capacitor balancing in each PWM cycle allows the use of low-value capacitors even in high-power applications. The modular and scalable design of MLIs facilitates expansion, maintenance, and fault diagnosis. These features make MLIs particularly beneficial in renewable energy systems, where they improve grid integration without bulky transformers and enhance overall system efficiency. MLIs contribute to smoother motor operation, reduced heating, and extended motor life in industrial applications, such as variable-speed drives. Power electronic converters are crucial in electrical drives, where faults such as open or short circuits can pose significant risks. Conventional MLIs frequently encounter faults in power switches, gate drivers, or wiring. Reliable fault tolerant MLI schemes usually involve over-rated or more reliable components, redundant designs, or automatic control strategy adjustments in case of partial converter failures. In this thesis, all proposed schemes are hybrid with cascaded H-bridge stages, inherently providing fault tolerance. A three-level fault-tolerant scheme is presented and experimentally validated. If a fault occurs in any switch within the cascaded H-bridge stage, the inverter can continue to operate as a two-level inverter at full-rated output power. The faulty part can be seamlessly isolated during operation without transients in the phase voltage or current, maintaining the power supplied to the load before and after fault isolation. Experimental results for both standard and fault conditions are provided. Many three-level and five-level inverter topologies exist, but most can only achieve a peak phase fundamental output voltage of 0.577Vdc in the linear modulation region. Increasing the peak phase fundamental voltage to 0.637Vdc in six-step mode introduces lower-order harmonics in the output phase voltage, leading to unwanted vibrations, torque pulsations, and harmonic losses, restricting the motor’s linear speed range to 90.5% of its full base speed. This research proposes three hybrid MLI topologies that extend the linear modulation range to the full base speed of the motor, generating a maximum peak fundamental phase voltage of 0.637Vdc without lower-order harmonics in the output phase voltage. This is achieved by boosting the DC-link voltage with a charged capacitor and controlling the capacitor voltage using redundant vectors during PWM operation. These schemes feature inherent capacitor balancing, eliminating the need for additional pre charging circuits. By extending the modulation range linearly to the full base speed from 0.577Vdc to 0.637Vdc, the phase voltage remains free of lower-order harmonics. This extension retains the multilevel structure in the overmodulation region, unlike the six-step mode. Additionally, all three proposed topologies are cascaded hybrid inverters, offering fault tolerance. They continue to operate as inverters with reduced levels in the event of faults in the H-bridge stage. The inverter operation and capacitor balancing technique are thoroughly analyzed, with simulation and experimental results for unity and non-unity power factor loads presented in both steady and transient states. The second chapter introduces a hybrid three-level inverter topology, a cascade of two-level and capacitor-fed H-bridge stages, extending its linear modulation range and experimentally validating its fault tolerance. The third and fourth chapters focus on hybrid five-level inverters. The third chapter extends the linear modulation range of an existing hybrid five-level inverter topology, while the fourth chapter proposes a novel hybrid five-level inverter topology, enhancing performance and reducing voltage stress across power switches. Performance validation of all proposed topologies was initially conducted through simulations in SIMULINK. Laboratory prototypes were then developed using a DSP (TMS320F28335D) and an FPGA (Xilinx SPARTAN-3) for control and PWM pulse generation. The topologies were experimentally tested for steady-state and transient performance with a three-phase induction motor load. The proposed inverters offer significant advantages, including a single DC power supply, extended linear modulation range, fault tolerance, reduced voltage stresses, and inherent capacitor balancing, making them ideal for electric vehicles, medium voltage, and high-power motor drive applications. Detailed results and analyses are presented in this thesis.