| dc.description.abstract | RF over fibre (RoF) based communication system combines features of mm-wave and optical fibre communication. The RoF-based system has the advantage of both optical fibre systems (such as high bandwidth, signal transparency, low-loss and lesser weight of optical fibre) and RF systems (such as mobility and distribution). This RoF transceiver can be made more efficient by combining it with beamforming techniques and reconfigurability. Spatial beamforming techniques help in minimizing the interference in the wavefront by active beam alignment in the transmit and receive paths. Even though, the realization of transceiver chip with electronics and optical circuits is very challenging, it can potentially be realized in future using silicon-photonics technology. This technology is commercially viable for mass-production, since it is compatible with matured CMOS technology. This dissertation presents different design techniques and architectures of electronic components, such as, phase-shifter, attenuator, SPDT switch and TIA, for improving the performance of RoF based phased array transceiver using CMOS/BiCMOS technologies.
The trade-offs in the beamforming architectures have been first discussed in terms of their performance, circuit design complexity and realization cost. Overview of the functionalities and implementation of each electronics and photonics component used in the RoF based phased array transceiver has been presented. The research objectives have been outlined based on the available literature and implementation strategy.
The design of a 7-bit S-band digital passive phase shifter realized using CMOS 65 nm technology is first described. This phase-shifter utilizes novel switched delay network- based topologies for 5.625 degree and 2.8 degree phase bit, along with modified switched filter topologies for other phase-bits. The experimental results of the fabricated chip have shown 7-bit performance with an average insertion loss, root mean square (RMS) phase error and RMS amplitude error of ≤ 11 dB, ≤ 2.0 degree and ≤ 0.6 dB, respectively, with S11 ≥ 7.5 dB and S22 ≥ 14.5 dB across the target frequency band of 2.6 to 3.2 GHz. In addition, design techniques for the realization of broadband switched type IF passive phase-shifter have been presented. These techniques include custom design of a two-metals inductor, a cross-coupled inductor with centre taping and setting the DC bias at RF input/output to 0 V. Design and EM simulation results of a 22.5 degree passive phase-shifter, with and without these broadband techniques, have been discussed for demonstrating their validity. The proposed topology has shown broadband phase-shifter response across 2.5-to-8.0 GHz, with RMS phase error, amplitude error and insertion loss of < 0.78 degree, < 1.26 dB, and < 1.52 dB, respectively, with S11/S22 > 9.2 dB.
The design details and simulations of an 8-bit S-band digital passive attenuator, and proposal of a bit topology selection algorithm to achieve low RMS phase error and low amplitude error have been described next. This attenuator has been designed by using new phase compensated Π−, T−and T −bridge attenuator bit topologies for 32 dB to 0.25 dB attenuator bits, and adopting the bit topology selection algorithm. This attenuator has been designed using 65 nm CMOS technology, and its performance has been characterized with the help of exhaustive post-layout simulation in 2.8 GHz to 4.0 GHz frequency band. The designed attenuator has demonstrated significant improvement in performance with 8-bit attenuation accuracy, insertion-loss of ≤ 5.1 dB, RMS amplitude error of ≤ 0.1 dB, RMS phase error of ≤ 0.78 degree, and S11/S22 > 12 dB in 2.8 GHz to 4.0 GHz frequency band.
Thirdly, the design details of a fully differential Ka-band single-pole double-throw (SPDT) switch with virtual grounding, realized using 0.13 μm SiGe BiCMOS technology, have been discussed. This SPDT switch with fully differential topology inherently offers cancellation of common-mode disturbance and has high P−1dB. Further, an asymmetri- cally tapered inductor utilization has been introduced in this SPDT switch with a normal spiral inductor to reduce the layout area of the SPDT switch. Experimental results of the fabricated differential SPDT switch with normal spiral inductor has exhibited the best insertion loss of 2.9 dB and an isolation of -39 dB in 25 GHz to 40 GHz frequency-band, with input P−1dB of 12.6 dBm at 34 GHz and 0.47 mm2 chip-area. Compact differential SPDT switch with asymmetrically tapered inductor has occupied an area of 0.11 mm^2 in the layout and demonstrated superior insertion loss of 1.8 dB and isolation of -39 dB in the same frequency-band with improved input P−1dB of 14.1 dBm at 34 GHz. For further improving the input P−1dB of this SPDT switch, a design of SPDT switch design 3 with pass-gate switch configuration has been presented next. In this design 3, pass-gate tran- sistor terminals biasing is set to 0 V through a 20 KΩ resistance for reducing variations in device parasitics. This SPDT switch has demonstrated a minimum insertion-loss of 1.29 dB, maximum isolation of 41.2 dB and S11/S22 better than 12 dB across the frequency band of operation. This SPDT switch has also shown input P1dB of 15.4 dBm with a layout area of 0.11 mm^2
Design trade-offs, mathematical analysis and circuit architecture of a new low-noise, broadband single-stage transimpedance amplifier (TIA) using 130 nm bipolar complemen- tary metal-oxide-semiconductor (BiCMOS) has been next presented in detail. This TIA is designed as a Common-emitter (CE) shunt-shunt feedback topology with active inductor peaking, and scalable bandwidth enabling better noise, gain and driving capability. The validity of the active inductive peaking and mathematical analysis has been proved with the help of simulations and measurement results. The experimental results of Ku-band TIA (10 MHz to 14 GHz) designed using this architecture have shown a transimpedance gain of 53.2 dBΩ, input-referred current noise of 16.8 pA/√Hz with power consumption of 9.8 mW. Further, another TIA covering K- and Ka-bands (10 MHz to 35 GHz) has been presented to demonstrate the architecture’s adaptability for higher bandwidth. This K-and Ka-bands TIA has demonstrated a transimpedance gain of 33.4 dBΩ, input-referred current noise of 29.4 pA/√Hz with a power consumption of 28.1 mW in the post-layout simulation results, and occupies the same chip area as that of Ku-band TIA, i.e., 0.1 × 0.21 mm^2.
Finally, the feasibility of a 35 GHz RoF communication link has been presented with the help of an experimental demonstration of a 2D integrated RoF photonic transmitter link. This demonstration has addressed the challenges associated with 2D integration. This test-jig has been assembled on a Kovar substrate using a silicon-photonics microring modulator die, driver amplifier die, and interconnected using 50 Ω transmission line. The integrated transmitter link has demonstrated the measured electro-optical (S21) band- width of 35 GHz, the maximum gain of 12.4 dB, RF matching at driver amplifier input in the range of -5 dB to -42 dB and optical matching at microring modulator input in the range of -8 dB to -21 dB for 50 Ω load across 35 GHz frequency bandwidth. | en_US |
