| dc.description.abstract | Thin-film transistor technology based on non-crystalline materials forms the workhorse
of large area electronics applications including display systems, sensor systems and novel
technologies including flexible electronics. A successful development and commercialisation
of any technology requires a thorough understanding of the physics and reliability
concerns revolving around that technology. Electrostatic discharge (ESD) is one of the
major reliability concerns in microelectronics industry and can plague the device development
at many stages. It is a high-field high-frequency phenomenon and involves charge
transfer from one body to another. Studying ESD behaviour also leverages studies on
non-equilibrium electro thermal behaviour of the device and highlights various high-field
effects taking place in the device under test. In this work, we study the ESD behaviour of
thin-film transistor technologies based on hydrogenated amorphous silicon (a-Si:H) and
organic materials.
In the first chapter, we give an overview of the current level of understanding vis-a-vis the
ESD behavior of non-crystalline materials based thin- lm technology platform. A brief
discussion on the ESD behavior and testing methodology of conventional silicon technology
is presented. We also discuss ESD issues in TFT technology, current roadblocks and
possible solutions. We also discuss other reliability issues that plague TFTs. Following
this, a detailed description, based on earlier studies, of the physical behavior, failure
characteristic and degradation behavior of hydrogenated amorphous silicon, metal oxide
based semiconductors, poly silicon and organics based semiconductors is presented. A
review of plethora of strategies that have been employed to enhance the ESD robustness
in these technologies, including novel designs and architectures is presented.
In the second chapter, we discuss, in detail, physical behavior of inverted staggered hydrogenated
amorphous silicon TFT technology under ESD stress conditions. Using electrical and optical techniques, device failure and TLP quasi-static I-V characteristics are discussed.
Raman spectroscopy is utilized to study any material variations with the stress
levels. Finally, we move on to discuss the impact of device design including impact of
device dimensions and architectural parameters including top passivation on the ESD
behavior of these devices.
As we move on to the third chapter, we study the device degradation of a-Si:H thin-film
transistors under the application of high field stress. I-V, C-V and raman spectroscopy
measurements are used to investigate the degradation mechanism. Threshold voltage
shift under moderate and high electric field in investigated and spatial variance of degradation
mechanism along the channel length is discussed. Variation of material properties
is studied. We also discuss the role of self-heating in device degradation and is studied by
varying the pulse width of stress pulses in nanoseconds range. We also discuss the performance
recovery mechanism through the application of thermal and gate bias anneal and
this has been investigated through a recursive cycle of stress- anneal and measurements.
Following these investigations, we report and study the phase transition behavior of
a-Si:H TFTs under high-field nano-second timescale electrical stress. This transition
is confirmed through a series of measurements including Raman Spectroscopy, Atomic
force microscopy, Scanning electron microscopy, Transmission electron microscopy and
I-V measurements. The observed behavior is attributed to avalanche generation, optical
phonon generation and localisation. We also study the case of drain underlap devices and
study how their behavior is different from conventional TFTs. Impact of pulse condition
including pulse width and channel dimensions on the onset of phase transition is also
explored. Interestingly, it is also found that the discussed phase transition mechanism
yields resultant nc-Si of quality at par with commercial methods.
At this point in the thesis, we have investigated the ESD and high-field reliability behavior
in a-Si:H TFTs. In the next chapter, we move our discussion towards incorporating
device architecture that improves the ESD robustness of a-Si:H TFT technology. The
discussed architecture is shown to improve the ESD robustness by 4-5 times with the
same area. We also investigate the physics of device behavior and explore the impact of
technological parameters on failure behavior. We also take a look at the pre breakdown
degradation behavior of this architecture. Finally, we take a look at the ESD behavior
of thin-film resistors.
In the next chapter, we discuss the ESD behavior of a-Si:H based diode-connected transistors. We discuss the ESD behavior as a function of stressing conditions, device dimensions
and on the application of negative ESD stress. We then discuss the instability behavior
of a-Si:H based diode-connected TFTs. This investigations assumes importance due to
the important role of these devices in switching and ESD protection circuits. Variations
in cut-in voltage of device under test is studied with application of the stress. DC I-V
measurements are used to explore the degradation behavior and shift in cut-in voltage as
a function of ambient temperature, pulse width and voltage levels is investigated. It is
also found that the degradation mechanism in these devices is different from the case of
conventional TFTs.
Till this point in this thesis, discussions have revolved around the behavior of a-Si:H
based devices. However, large area electronics based on novel classes of materials have
gained significant traction in recent years. One such class of materials is that of organic
semiconductors. Organic semiconductors also offer the advantage of cheaper fabrication
with lower thermal budget. This has enabled their application in flexible and printable
electronics. In the course of this work, we focus on pentacene as the model organic material.
In the seventh chapter, we discuss the ESD failure of pentacene channel OTFTs.
Charge transport mechanism at nano-second timescale is studied and orders of magnitude
difference are observed in DC and ESD timescales. Device failure is investigated through
SEM imaging and EDX spectroscopy. We also discuss the impact of self-heating behavior
along with the impact of channel dimensions and stressing conditions. It is observed that
the device failure is not due to semiconductor breakdown. We also study the impact of
introduction of self-assembled monolayer on charge transport and ESD failure. Finally,
we discuss the device failure for the case of high-voltage pentacene OTFTs with a 1μm
thick dielectric.
Following the investigation of ESD behavior of pentacene based OTFTs, we report high
frequency behavior of pentacene channel OTFTs through the exploration of transient
voltage waveforms in the eighth chapter. Pentacene OTFTs present a delayed response
to the applied signal due to the parasitic impedance involved. The device behavior is affected
by the bias stress effect and self-heating effect. It is also shown that as the channel
length increases, device responds faster. However, this behavior is shown to be present
at smaller channel length and as the channel length increases, the device impedance increases
and response gets slower. | en_US |
