dc.contributor.advisor | Nandy, S K | |
dc.contributor.author | Baral, Pushpa | |
dc.date.accessioned | 2022-01-04T05:40:21Z | |
dc.date.available | 2022-01-04T05:40:21Z | |
dc.date.submitted | 2021 | |
dc.identifier.uri | https://etd.iisc.ac.in/handle/2005/5577 | |
dc.description.abstract | Manycore heterogeneous architectures are becoming the promising choice for high-performance computing applications. Multiple parallel tasks run concurrently across different processor cores sharing the same communication and memory resources, thus providing high performance and throughput. But, with the increase in the number of cores, the complexity of the system also increases. Such systems provide very limited visibility of internal processing behaviour. This poses a challenge for a software developer as it is difficult to monitor the program in execution. Monitoring the program behaviour is required for exploiting the architecture to the maximum, debugging, security, performance analysis, and so on.
REDEFINE is one such macro dataflow execution based manycore co-processor designed to accelerate the compute-intensive part of an application. In this work, we propose a static and dynamic monitoring framework in REDEFINE. First, we present a software instrumentation based approach to generate the execution traces with negligible hardware overhead. The generated trace data is processed through an offline analysis tool to get the execution graph. This graph can be utilized to analyse the program behaviour statically. Although this approach is flexible and easy to implement, the offline analysis might result in delayed detection of any unexpected program behaviour. To address this, we then present a run-time monitoring framework. In this approach, a separate hardware monitoring unit runs in parallel to the processor core. The monitor is programmed with the monitoring graph obtained from static analysis of the program binary. It matches the instructions executed with the corresponding information in the monitoring graph and flags any unintended program behaviour. This aids in the identification of any intrusion or attack that alters the control flow integrity of the program executed and further helps in the realisation of a secure computing platform that is a primary requirement today in the area of 5G network processing, autonomous vehicles and avionics applications. | en_US |
dc.language.iso | en_US | en_US |
dc.rights | I grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part
of this thesis or dissertation | en_US |
dc.subject | Manycore Architecture | en_US |
dc.subject | RISC V processor | en_US |
dc.subject.classification | Research Subject Categories::TECHNOLOGY::Information technology::Computer science | en_US |
dc.title | Static Analysis and Dynamic Monitoring of Program Flow on REDEFINE Manycore Processor | en_US |
dc.type | Thesis | en_US |
dc.degree.name | MTech (Res) | en_US |
dc.degree.level | Masters | en_US |
dc.degree.grantor | Indian Institute of Science | en_US |
dc.degree.discipline | Engineering | en_US |