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    • Division of Electrical, Electronics, and Computer Science (EECS)
    • Computer Science and Automation (CSA)
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    IO Pattern Aware Methods to Improve the Performance and Lifetime of NAND SSD

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    Thesis full text (1.398Mb)
    Author
    Arpith, K
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    Abstract
    Modern SSDs can store multiple bits per transistor which enables it to have higher storage capacities. Low cost per bit of such SSDs has made it a commercial success. As of 2018, cells with an ability to store three bits are being widely used, with Intel and Micron just announcing even the availability of the first commercial SSD with quad level cells. However, such high-density SSDs suffer from longer latencies to write and read data, resulting in reduced throughputs, when compared to ash memories that store a single bit per cell. Also, they suffer from reduced reliability. Mechanisms to detect bit errors and prevent data loss add to performance overheads. In this thesis, we propose two system-level solutions, that use the knowledge of IO patterns of the workload to improve the performance and lifetime of NAND based solid state drives. The first part of the work proposes to combine various page types in a wordline to a single logical page called a Melded-Page. This improves the read performance of an SSD by mitigating the overheads involved in the read operation. Using this method, we achieve performance improvements of up to 44% on distributed workloads that use Hadoop Distributed File System (HDFS). Second, to improve the write performance and lifetime of an SSD, we propose a modifi ed programming scheme called Hot Page Aware Relaxed Program Sequence scheme. Constraints are put in place to ensure that a lower signi ficant bit is invalidated before programming a higher signi ficant bit. Experimental results show an average improvement of 56% in the performance of the SSD when compared to the existing program sequence scheme. We also observe a reduction in the number of pages backed up by an average of 85%. When compared to methods that use dynamic SLCs, the proposed scheme can reduce the number of block-erases by an average of 61%.
    URI
    https://etd.iisc.ac.in/handle/2005/5376
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    • Computer Science and Automation (CSA) [393]

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