A Novel Algorithm-Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification

Abstract

In EDA industry, design-under-test (DUT) is a pre-silicon digital design which is still undergoing testing phase. We perform functional-verification of a DUT to verify whether the DUT conforms to the specifications. Functional verification has been pre-dominantly performed through simulation of a DUT. However, their execution speed rapidly degrades when DUT size reaches 100 million gates. To overcome this bottleneck, the EDA industry is increasingly adopting “hardware-accelerated simulation platforms”, which are classified as simulation-accelerators, emulators and FPGA prototypes. These methodologies perform functional verification by synthesizing and implementing the DUT on a verification platform. Hence, the existing functional-verification flows give rise to the issue of synthesizing and implementing every new or revised DUT on the verification platform. A functional-verification flow, “executing” the DUT directly on the verification platform, will avoid the overhead involved in performing hardware synthesis and implementation of every new or revised DUT. In our thesis, we present EX-DRIVE, an execution-driven functionalverification system, which performs functional-verification of a DUT without the need for hardware synthesis and implementation of the DUT, offering significant improvement in functional-verification time. Minimal design set-up time through adaptation of Discrete Particle Swarm Optimization, convex and heuristic based partitioning mapping schemes, is an added feature of the proposed system. We show that the proposed functional-verification system achieves significant improvement in verification performance over industry standard simulators and emulation platforms. We have explored the design space of EXDRIVE for various sizes of NIHC fabric and the proposed partitioning and mapping algorithms. In order to explore the design space of EXDRIVE for the proposed partitioning and mapping algorithms, we adopt a NIHC fabric comprising a 3 ∗ 3 array of HC’s whereby each HC consists of a 5 ∗ 5 array of CU. Similarly, to explore the design space of EXDRIVE for various sizes of NIHC fabric, we adopt the convex partitioning scheme