Towards Logic Circuit Applications Using Solution Processed CNTs

Abstract

With Silicon transistor technology reaching its practical limits, e orts to replace Si with new materials with better electronic transport properties have gained considerable at- tention. Single-walled carbon nanotubes (CNTs) are one of the promising materials for transistors operating beyond 10 nm node technology because of their excellent electronic, thermal and optical properties. There have been many reports on CNTs for various ap- plications including logic circuits, sensors etc. However, field effect transistors (FET) made of CNTs generally exhibit p-type behaviour. In order to realize complementary logic circuits, both p- and n-FETs are necessary. There have been reports demonstrating logic circuits using only p-type CNTFETs as well as complementary structures i.e., both p- and n-CNTFETs. In most cases, the n-CNTFETs used in the complementary logic circuits are fabricated using rare earth metals for source/drain contacts which are not suitable for large-scale fabrication. Hence, there is a need to develop a more practical approach to fabricate n-CNTFETs/Complementary logic circuits. Another key issue with CNTFET technology is the development of suitable contact electrode material that gives low barrier heights for both p- and n-type CNTFETs. In the first part of the thesis, two methods have been explored to fabricate n- CNTFETs viz., (a) Polymer doping and (b) Surface passivation using Silicon Nitride (SiNx) films. Both the methods resulted in air-stable n-CNTFETs using back-gate ge- ometry. However, the polymer doping method was found to be unsuitable for top-gated n-CNTFETs. In the surface passivation method, SiNx lm covers the surface of CNT- FETs, preventing the CNTs from exposure to atmospheric oxygen, thus, making them n-type. This method of obtaining n-type CNTFETs is advantageous as SiNx lm serves both as a passivation layer and as a top gate dielectric. Thus, the multifunctional nature of SiNx film reduces fabrication complexity. In order to fabricate top-gated n-CNTFETs, SiNx thin film is deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The developed SiNx films have been characterized for their optical and dielectric properties using Ellipsometry and electrical measurements such as C-V and I-V respec- tively. The SiNx films with 15 nm thickness have a refractive index of 1.96, a dielectric constant of 5 and current leakage density of 10ð€€€6 A/cm2 at 1 MV/cm. XPS measure- ments have been carried out to determine the compositional analysis which indicates the stoichiometry of the films is Si3N4. Using 15 nm thick SiNx films as a gate dielectric, top-gated n-CNTFETs have been fabricated. These top-gated n-CNTFETs have an Ef- fective Oxide Thickness (EOT) of 10 nm and operating gate voltages within 2.5 V that resulted in mobilities of 15 cm2/Vs and subthreshold slopes of 180 mV/dec. Using two such n-CNTFETs, a logic inverter was fabricated and evaluated, thus demonstrating the suitability of PECVD grown SiNx films as gate dielectric for logic circuit applications. In the next part, top-gated p-CNTFETs have been fabricated using electron beam evaporated HfO2 (30 nm thick) as a gate dielectric. The fabricated top-gated p-CNTFETs have an EOT of 6.5 nm, operating gate voltages within 2.5 V, mobilities of 35 cm2/Vs and subthreshold slopes of 130 mV/dec. These p-CNTFETs are then integrated with n-CNTFETs and demonstrated a complementary logic inverter with a dc gain as high as 6.7 and operating voltages within 1 V. In this approach, both the dielectric lms (HfO2 for p-CNTFETs and SiNx for n-CNTFETs) have been deposited at a low temperature making the process suitable for region-selective deposition of dielectric films. This fabri- cation approach is CMOS compatible and is suitable for large-scale fabrication since the usage of rare earth metal contacts is avoided. The last part of the thesis deals with the issue of barrier heights at CNT-metal junction. One of the problems in the electronic performance of CNTFETs has been the high barrier height of CNT - metal contact forming a Schottky junction which results in low ON currents. Low Schottky barrier contacts are possible for both p-type and n-type CNTFETs, using different metals e.g. Palladium for p-type and Scandium for n-type CNTFETs. As mentioned earlier, the metals used for n-type CNTFETs are rare earth metals and may not be suitable for large-scale production. On the other hand, graphene is considered to be an excellent contact material for CNT devices because of their homogeneous carbon junction and better wettability to CNTs. In this work, both p- and n-type CNTFETs are fabricated and characterized by utilizing graphene as a contact electrode material. Using temperature dependent I-V measurements, it is shown that the barrier height at CNT - graphene junction is close to zero for both electron and hole transport. This indicates the suitability of graphene as an Ohmic contact material for complementary logic circuits using CNTFETs. It has also been observed that there is no correlation between the barrier height at the CNT - graphene junction and thickness of graphene.