Hardware Emulation of a Long Transmission Line by High Frequency Power Electronic Converter for the study of Switching Transients
To ensure smooth functioning of the grid, the reliability and robustness of the power system equipment needs to be precisely evaluated during their development process. But direct on- eld tests of most of the equipment are not possible. This urges for having an emulated environment which will operate in real-time thereby capturing all the physical phenomenon of the Hardware Under Test (HUT). The control and pro- tection equipments are generally tested by Hardware-In-The-Loop (HIL) technology, where a Real-Time Simulator (RTS) implemented on a digital platform, interacts with the HUT in real-time. Also high power rating devices can be tested by adopting a di erent technology known as Power-Hardware-In-The-Loop (PHIL), where a Power Amplifier (PA) acts as the interface between the RTS and HUT. The most expensive component of the PHIL is the general purpose RTS like Opal-RT or RTDS. To reduce the cost, RTS can be made application speci c. This Application Specific-Real-Time Simulator (AS-RTS) and the PA collectively simulating the test environment for the HUT is termed as the Hardware Emulator (HE) of that particular application. Being the fundamental component of the power system, HE of transmission line is required to bridge the gap between the source and load emulators. Hence a programmable type of Transmission Line hardware Emulator (TLE) needs to be developed which will have the exibility of emulating transmission line with varying line parameters. The general architecture of a TLE comprises of two major components, namely, Ob- server and Power Ampli er, where the AS-RTS for the TLE is termed as the Observer. With the line end voltages as the input, the Observer solves the emulated line model in real-time and estimates the line end currents which are then tracked by the PA by controlling its output currents. Utilizing the exibility of controlling power electronic converters, the PA is comprised of two back-to-back 3 Voltage Source Converters (VSCs) operating under closed loop current control mode. Based on similar archi- tecture, emulation for short lines during steady state and 3 short-circuit faults are reported in literature, where the transmission line is modeled as a lumped resistor in series with a lumped inductor. For analyzing the performance of the grid at the transmission level, it becomes necessary to consider long lines. Emulation of a dis- tributed parameter lossy transmission line during steady state and 3 faults using Method of Characteristics (MOC) has also been performed. However with MOC, the computational burden of the Observer signi cantly increases. i Hardware emulation of energization of a long transmission line is not addressed in either of the previous work. Simultaneous switching of all the phases of one end of the transmission line with a shunt reactor connected at the other end has been studied in this work and the transients in the source end line currents during the instant of switching has been emulated by the developed TLE. When an unenergized transmission line is suddenly connected to a voltage source, high frequency transients appear in the line currents due to the travelling wave phenomenon before the at- tainment of steady state. After studying di erent line models for lossy long lines, a travelling wave based numerical solution is identi ed which can be solved by the Ob- server in real-time. The Observer is implemented on a Zynq System-On-Chip (SoC) platform from Xilinx. As the transient current contains high frequency components, the switching frequency of the VSC should be su ciently high in order to minimize the phase loss of the current control loop of the PA. So a Silicon Carbide (SiC) based power electronic converter has been designed and fabricated to implement the PA of the TLE. A comprehensive analysis has been made to choose the switching fre- quency of the power electronic converter and the sampling frequency of the Observer, while adhering to the power and digital hardware constraints (maximum switching frequency limit, clock speed, etc.). Further, the hardware topology for the imple- mentation of the TLE as well as scaling of the actual transmission line to laboratory level emulator without compromising on the system dynamics has been presented. Finally the relevant simulation waveforms are matched with the experimental results performed on the developed hardware prototype of the TLE, thus validating the TLE test bench setup.
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