Efficient Dislocation Reduction Methods for Integrating Gallium Nitride HEMTs on Si

Abstract

Gallium Nitride (GaN) and its alloys with InN and AlN, the III-nitrides, are of interest for a variety of high power-high frequency electronics and optoelectronics applications. However, unlike Si and GaAs technology that have been developed on native substrates, III-nitride devices have been developed on non-native substrates such as Si, sapphire and SiC. This is because bulk cheap native III-nitride substrates are unavailable. Among the known substrates, III-nitride technology development on Si is desirable because of its large substrate size and low cost. However, the large lattice and thermal expansion mismatch between the III-nitrides films and Si substrate leads to a high level of dislocations, 1010 cm-2, and tensile stress which results in cracking. For successful integration of crack free and low dislocation density GaN on Si various kinds of transition layer schemes are used that help to incorporate a compressive growth stress to neutralize the tensile thermal mismatch stresses and also to reduce dislocation densities to levels required by devices. These transition schemes, ranging from 400 nm to 7 m, involve the use of graded AlGaN layers, high/low temperature interlayers and superlattices. The aim of the research described in this thesis was a systematic comparison of the different transition layer schemes currently used with the objective of increasing the efficiency of integrating device quality, crack free, low dislocation density, <109 cm-2, GaN with Si. A metal organic chemical vapor deposition equipped with an in-situ stress monitor was used for growth. Transmission electron microscopy was used for quantitative measurement of dislocation density. The research shows, for the first time, that all transition layer optimization depends critically on the Si surface made available for growth of the first AlN layer. It needs to be optimally cleaned such that it is oxide free and smooth. A quantitative TEM comparison of various currently used transition layer schemes shows that while they have interesting mechanistic differences, they are not very different in their dislocation reduction efficiency. All of them yield a final dislocation density in a probe GaN layer of 1-3×109 cm-2. In contrast, a combination of Si doping and compressive growth stress has a synergistic effect on dislocation reduction. A simple 210 nm transition layer based on this understanding, the lowest reported yet, yields GaN layers that are crack free and have lower <1x109 cm-2 dislocation density, than those obtained by the aforementioned more complicated schemes. High electron mobility transistor characteristics performance on the probe GaN layers obtained on these transition layers supports the structural observations above.