Browsing Centre for Nano Science and Engineering (CeNSE) by Subject "design-under-test"
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A Novel Algorithm-Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification In EDA industry, design-under-test (DUT) is a pre-silicon digital design which is still undergoing testing phase. We perform functional-verification of a DUT to verify whether the DUT conforms to the specifications. Functional ...