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    Browsing Centre for Nano Science and Engineering (CeNSE) by Advisor 
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    • Centre for Nano Science and Engineering (CeNSE)
    • Browsing Centre for Nano Science and Engineering (CeNSE) by Advisor
    •   etd@IISc
    • Division of Interdisciplinary Research
    • Centre for Nano Science and Engineering (CeNSE)
    • Browsing Centre for Nano Science and Engineering (CeNSE) by Advisor
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    Browsing Centre for Nano Science and Engineering (CeNSE) by Advisor "Nandy, S K"

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      • Accelerated and Accurate Alignment of Short Reads in High Throughput Next Generation Sequencing [NGS] Platforms 

        Natarajan, Santhi
        The genome of an organism encompasses the unique set of genetic instructions for every individual in a species. The genome, in totality, guides the course of evolution, development, genetic and epigenetic growth factors ...
      • ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor 

        Kala, S (2016-09-09)
        The rapid advancements in semiconductor technology have led to constant shrinking of transistor sizes as per Moore's Law. Wireless communications is one field which has seen explosive growth, thanks to the cramming of more ...
      • Energy Efficient Flexible Baseband Processing for Mobile and Cognitive Radios 

        Pradhan, Ashish Kumar
        Wireless communication has become an integral part of human life, and one of the dominating applications in today’s world. Mobile communication devices are the largest consumer electronic group in terms of volume. In 2007, ...
      • Hardware-Software Co-Design Accelerators for Sparse BLAS 

        Ramesh, Chinthala
        Sparse Basic Linear Algebra Subroutines (Sparse BLAS) is an important library. Sparse BLAS includes three levels of subroutines. Level 1, Level2 and Level 3 Sparse BLAS routines. Level 1 Sparse BLAS routines do computations ...
      • A Novel Algorithm-Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification 

        Mahapatra, Ipsita Biswas
        In EDA industry, design-under-test (DUT) is a pre-silicon digital design which is still undergoing testing phase. We perform functional-verification of a DUT to verify whether the DUT conforms to the specifications. Functional ...
      • Reconfigurable Accelerator for High Performance Application Kernels 

        Das, Saptarsi
        Accelerating high performance computing (HPC) applications such as dense linear al- gebra solvers, mesh computations, stencil computations requires exploiting parallelism that is resident in loops. Typically these loops ...

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