A Scalable, Physics-Based Compact Model for Nano-Scale STI-Bounded SCRs in ESD Protection Applications

Abstract

Electrostatic Discharge (ESD) reliability has emerged as a critical challenge in modern Integrated Circuits (ICs), especially as technology scaling pushes devices into nanoscale regimes with heightened sensitivity to high-voltage, high-current transients. Traditional ESD protection methodologies are no longer sufficient to guarantee safe operation, necessitating a deeper, physics-driven approach to device modeling. This work presents a comprehensive investigation of the transient behavior and compact modeling of shallow trench isolation (STI)-bounded nanoscale Silicon-Controlled Rectifiers (SCRs), a widely adopted ESD protection element in advanced CMOS technologies. Combining high-bandwidth Transmission Line Pulse (TLP) measurements with detailed 3D Technology Computer-Aided Design (TCAD) simulations, this study identifies and analyzes five critical segments of SCR behavior under ESD stress: the trigger point, turn-on dynamics, holding behavior, voltage overshoot, and failure threshold. Each segment is physically interpreted and linked to underlying carrier transport, impact ionization, and thermal feedback mechanisms. Special attention is given to avalanche breakdown and subsequent conductivity modulation, which are shown to be time-dependent and necessitate accurate transit-time modeling. The study also captures the role of internal resistive regions in shaping the holding voltage and discusses how these regions can be tuned to ensure safe post-trigger operation. A scalable, physics-based compact model is developed that accurately reproduces all five operating regimes using a minimal set of physically meaningful parameters, ensuring applicability across technology nodes and compatibility with circuit-level transient simulations. The model also captures overshoot effects driven by displacement current under fast transients, as well as thermal failure mechanisms arising from localized Joule heating and impedance collapse. Overall, this work addresses key gaps in existing SCR modeling approaches and provides a robust framework for predictive, simulation-ready ESD design in advanced ICs.