Investigations on hybrid multilevel power converter topologies and control schemes for AC drives

Abstract

Multilevel power converters have emerged as an attractive choice for high?power medium? and high?voltage applications such as high?power AC drives, active power filters, reactive power compensation, HVDC transmission, FACTS devices, etc. Compared to traditional two?level converters, multilevel converters offer significant advantages such as enhanced output?voltage quality at low switching frequencies, low electromagnetic interference, low voltage stress on semiconductor switches, reduced voltage derivative, reduced common?mode voltage, higher efficiency, etc. At higher numbers of voltage levels, the pulse?width?modulated staircase waveform generated by a multilevel inverter approximates a sinusoidal waveform, thereby eliminating the need for expensive and bulky filters in many applications. Furthermore, in many high?voltage applications, the transformer used for stepping up voltage can be eliminated, as multilevel inverters can generate high?voltage waveforms using low?voltage switching devices. However, as the number of voltage levels increases, the cost and complexity of multilevel inverter circuits increase, and reliability decreases due to the presence of a large number of components and associated control circuits. Hence, one of the main research directions in this field is the development of multilevel inverter topologies with fewer components, higher reliability, and higher efficiency. A number of multilevel converter topologies have been proposed since the introduction of multilevel power conversion in the late 1960s. Among these, three converters-namely the Neutral Point Clamped (NPC) inverter, the Flying Capacitor (FC) inverter, and the Cascaded H?Bridge (CHB) inverter-are known as conventional multilevel converters. All these topologies suffer from the disadvantages mentioned earlier. Attempts have been made to obtain higher output?voltage levels with fewer components by introducing new topologies such as asymmetric FC and CHB inverters. However, for real?power conversion, this has typically required limiting the range of operation or imposing more complex requirements on the DC source side. A higher number of voltage levels is always preferred in multilevel?inverter?fed AC drives, as it reduces harmonic distortion and eliminates the need for bulky and expensive filters. Higher voltage levels reduce dv/dt and common?mode voltage in the motor. High dv/dt causes overvoltage at the motor terminals and increases stress on motor insulation. High common?mode dv/dt also leads to high?frequency leakage currents, induced shaft voltage, and bearing currents, ultimately causing mechanical failure. By increasing the number of voltage levels, dv/dt can be significantly reduced. Increasing the number of voltage levels also reduces torque ripple. However, industries are reluctant to adopt higher?level converters due to increased component count, bulkiness, complexity, and reduced reliability. Therefore, there is a need to achieve higher voltage levels without substantially increasing component count or compromising system reliability. These issues are addressed in this research work. The focus of the research is the development of multilevel power converter topologies with fewer components, higher reliability, and higher efficiency, along with PWM control schemes for each topology. Another issue addressed is the elimination of common?mode voltage, which is one of the major causes of mechanical failure in high?power AC drives. The proposed hybrid multilevel converter topologies have enhanced fault tolerance. Two categories of topologies are proposed:

Open?end winding configuration, where both ends of the stator windings are supplied power. Single?sided supply scheme.

In both, significant reduction in the number of power components is achieved relative to conventional multilevel converters, especially at higher voltage levels. The PWM schemes developed are capable of maintaining floating?capacitor voltages irrespective of power factor or modulation index. Common?mode voltage elimination is achieved using special PWM techniques in some topologies. Although all topologies are experimentally validated on AC drives, their applications in grid?connected systems are also discussed. Chapter 2 presents a seven?level inverter topology for AC drives with open?end stator winding configuration. Two conventional three?phase two?level inverters and two floating?capacitor?fed H?bridges per phase are used. The floating capacitors are maintained at V_{dc}/6 using redundancy in switching states. A robust PWM scheme is used for capacitor?voltage balancing using a hysteresis controller. The topology has high reliability and can operate in three?level mode if any H?bridge fails. Chapter 3 introduces a nine?level inverter topology with open?end stator winding using asymmetric capacitor voltage levels (V_{dc}/4 and V_{dc}/8). Capacitor balancing algorithms ensure voltage regulation. The topology requires significantly fewer components than conventional nine?level topologies and offers high fault tolerance. Chapter 4 presents a five?level inverter using a single reduced DC source and special PWM for common?mode current elimination. The reliability features of earlier topologies are retained. Chapter 5 presents a hybrid multilevel converter topology using only one DC source and floating capacitors at asymmetric levels. It significantly reduces component count and capacitor count compared to FC converters, especially at nine levels and higher. The topology has high efficiency and fault?tolerance capabilities. Chapter 6 presents a hybrid five?level inverter with complete common?mode voltage elimination using SVPWM. It uses asymmetric floating?capacitor voltages and includes capacitor?voltage balancing. It can operate in 3?level or 2?level mode under faults. All proposed topologies and PWM schemes were simulated using MATLAB/Simulink and experimentally verified on a 5?HP induction?motor drive across the entire modulation range including over?modulation. Capacitor?voltage dynamics, motor control, and SVPWM were implemented on a TMS320F2812 DSP, while hysteresis control and switching logic were implemented on a SPARTAN?3 XC3S200 FPGA platform.