Modeling the electrostatics of symmetric double gate MOSFETs

Abstract

The continuous downsizing of Complementary Metal Oxide Semiconductor (CMOS) technology has resulted in drastic degradation of the performance of conventional MOS transistors. As a result, new transistor architectures need to be introduced in order to continue the rapid growth of the semiconductor industry. The Double?Gate (DG) transistor has emerged as one of the options for sub?45 nm technology nodes due to its inherent advantages such as the ability to use an undoped body, which alleviates mobility degradation and random dopant fluctuation problems encountered in conventional bulk MOSFETs. The DG MOSFET can also approximate a particular case of FinFET with only the side channels being active. Additional benefits such as ideal subthreshold slope, volume inversion, and near?ballistic drive current have also been reported for DG MOSFETs. The goal of this thesis is to investigate the electrostatics of symmetric Double?Gate MOSFETs, considering the effect of geometrical parameter scaling on the threshold voltage and subthreshold slope while taking quantum confinement and short?channel effects into account. In the first part of this thesis, an analytical model for Ultra?Thin?Body (UTB) symmetric Fully?Depleted (FD) Double?Gate (DG) MOSFETs is proposed for silicon film thicknesses in the 1 nm to 4 nm range. This model takes into account the crystal symmetry changes caused by structural distortions inherent in ultra?thin?body devices on the one hand and the local crystal potential superposed by a strong transverse electric field across the device on the other hand. First, an analytical expression for the electrostatic potential is proposed, using the full band structure of the channel material calculated from a 10?orbital sp砫?s* tight?binding method. The channel charge density is determined from the electrostatic potential. It is shown that the electrostatic potential and channel charge density predicted by the proposed model match very well with the numerical results obtained from the tight?binding approach. Similarly, the channel current, determined using the drift杁iffusion model, is shown to be accurate across all regions of transistor operation for SOI films in the 1 nm to 4 nm thickness range. In the second part of this thesis, we report on the threshold?voltage modeling of Fully?Depleted (FD) Double?Gate (DG) MOSFETs over a wide range of SOI film thicknesses using a self?consistent Poisson朣chr鰀inger solver (SCHRED). We define the threshold voltage (V_{\text{th}}) of symmetric FD Double?Gate (DG) MOSFETs as the gate voltage at which the center potential (?_c) saturates to ?_c(sat), and analyze the effects of oxide thickness (t_{\text{ox}}) and SOI film doping density (N_{\text{si}}) on V_{\text{th}}. The validity of this definition is demonstrated by comparing the results with the channel charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V_{\text{th}} definition electrically corresponds to a condition where the inversion layer capacitance (C_{\text{inv}}) is equal to the oxide capacitance (C_{\text{ox}}) across a wide range of SOI layer doping densities. Based on this, an analytical model with the criterion C_{\text{inv}} = C_{\text{ox}} is proposed to compute ?_c(sat), while accounting for band?gap widening due to quantum?confinement effects. This is validated through comparisons with the Poisson朣chr鰀inger solution. Further, we show that at the threshold?voltage condition, the electron distribution n(x) along the depth (x) of the SOI film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double peak away from the center of the SOI film, but still within the bulk region of the Silicon?on?Insulator (SOI) layer. In the third part of this thesis, we analyze the combined effects of size quantization and device?temperature variations (T = 50 K to 400 K) on the intrinsic carrier concentration (n_i), electron concentration (n), and thereby on the threshold voltage (V_{\text{th}}) for thin SOI film (t_{\text{si}} = 1 nm to 10 nm) based fully?depleted (FD) Double?Gate (DG) Silicon?on?Insulator (SOI) MOSFETs. As in the previous cases, the threshold voltage (V_{\text{th}}) is defined as the gate voltage (V_g) at which the channel center potential (?_c) begins to saturate (?_c = ?_c(sat)). It is shown that in the strong quantum?confinement regime (t_{\text{si}} < 3 nm), the effects of size quantization far override the effects of temperature variations on the total change in band gap (?E_g,eff), intrinsic carrier concentration (n_i), electron concentration (n), ?_c(sat), and the threshold voltage (V_{\text{th}}). On the other hand, for t_{\text{si}} > 4 nm, it is shown that size?quantization effects recede with increasing t_{\text{si}}, while the effects of temperature variations become increasingly significant. Through detailed analysis, a physics?based model for the threshold voltage is presented both for the undoped and doped cases, valid over a wide range of device temperatures, SOI film thicknesses, and doping densities. In both the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete?ionization effects, which are usually observed at lower device temperatures. The results are compared with the published work available in the literature, and it is shown that the present approach incorporates quantization and temperature effects simultaneously over the entire temperature range (50 K�0 K). We also present an analytical model for V_{\text{th}} as a function of device temperature (T). In the last part of this thesis, based on TCAD (Atlas) simulations, we report the effects of channel?length scaling on the electrostatics (Threshold Voltage (V_{\text{th}}), Subthreshold Slope (SS), and Drain?Induced Barrier Lowering (DIBL)) of undoped thin SOI?film FD symmetric Double?Gate (DG) Silicon?on?Insulator (SOI) MOSFETs, considering quantization effects. The threshold voltage (V_{\text{th}}) is determined as the gate voltage (V_g) at which the potential corresponding to the top of the source朿hannel barrier at the center of the SOI film (?_c) saturates to a value ?_c(sat). This ?_c(sat) in turn depends on the SOI film thickness (t_{\text{si}}), gate length (L_g), and drain voltage (V_d). This threshold voltage is also shown to correspond to the condition when the channel charge density (Q_i) reaches Q_t(T), marking the transition between weak and strong inversion. The threshold voltage is used to determine the DIBL parameter. Similarly, the subthreshold slope is also determined as the average of dV_g/d(log I_D) when V_g < V_{\text{th}} and ?_c < ?_c(sat). A device model is proposed for the threshold voltage (V_{\text{th}}), and it is shown that the threshold voltage is equal to the product of the saturated center potential (?_c(sat)) and the subthreshold?slope factor (?_g). This model is shown to be valid over a wide range of channel lengths (L_g) and SOI film thicknesses (t_{\text{si}}). In addition, for a given t_{\text{si}} and t_{\text{ox}}, the channel length (L_g) where the transition from short?channel to long?channel behavior occurs (L_g = L_{\min}) can also be predicted, based on the gate length where the second derivative of the threshold voltage (V_{\text{th}}) with respect to L_g is minimum, which is useful from a device?design perspective. Using the center?potential?based approach, the electrostatic parameters of the symmetric DG SOI MOSFET are determined and compared in the quantum?confinement and semiclassical cases. It is seen that quantum?confinement effects tend to further enhance short?channel effects and thus the electrostatic parameters in the quantum?confinement case degrade compared to the semiclassical case. It is also seen that L_{\min} in the quantum?confinement case is larger than in the semiclassical case. These results are explained through detailed 2?D analysis of the conduction?band energy. Further, it is also shown that the transverse electric field (gate to channel) is higher in the semiclassical case than in the quantum?confinement case, thus indicating that in the semiclassical case, the gate has much stronger control over the channel compared to the quantum?confinement case. Furthermore, a semi?empirical model is proposed for the subthreshold?slope factor, center?potential saturation, and therefore the threshold voltage in the undoped case. Finally, a generalized model is proposed to correlate the center potential, the source朿hannel barrier potential, subthreshold?slope factor, channel charge density, and the threshold voltage.