| dc.contributor.advisor | Narahari, Y | |
| dc.contributor.author | Aithal, Sooryanarayana K | |
| dc.date.accessioned | 2026-03-12T10:42:44Z | |
| dc.date.available | 2026-03-12T10:42:44Z | |
| dc.date.submitted | 1998 | |
| dc.identifier.uri | https://etd.iisc.ac.in/handle/2005/9290 | |
| dc.description.abstract | Product design and development constitute an important activity in any manufacturing firm. Designing an optimized product design process and an optimized fabrication process is an important problem in itself and is of significant practical and research interest. In this dissertation, we look into the Printed Circuit Board (PCB) design and PCB fabrication processes and investigate different ways in which the design lead time and the fabrication lead time can be minimized. Single class and multi class queuing networks constitute the modelling framework for our studies.
First, we present an IDEF3 (Integration Definition) process model and a stylized queuing network model of a PCB fabrication company and show how rapid performance analysis can be used to explore opportunities for accelerating the fabrication process. In particular, we show how effective input control, process control, and load balancing can reduce the lead time appreciably.
Next, we develop an IDEF3 process model and a probabilistic re entrant line model for a PCB design organization that involves multiple, concurrent design projects with contention for human/technical resources. We explore how the design lead times can be reduced using efficient scheduling, input control, load balancing, and variability reduction techniques.
The models presented are sufficiently generic and conceptual; their scope extends beyond PCB design and PCB fabrication processes. The models will be of much value in general for planning the design and fabrication of any generic product. | |
| dc.language.iso | en_US | |
| dc.relation.ispartofseries | T04406 | |
| dc.rights | I grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation | |
| dc.subject | Queuing Network Analysis | |
| dc.subject | Re-entrant Line Models | |
| dc.subject | Input Control and Load Balancing | |
| dc.title | Modeling and analysis of industrial design and fabrication Processes | |
| dc.type | Thesis | |
| dc.degree.name | MSc Engg | |
| dc.degree.level | Masters | |
| dc.degree.grantor | Indian Institute of Science | |
| dc.degree.discipline | Engineering | |