Sensitivity and Round off noise studies on signal processor based second order digital filters

Abstract

Digital filters are invaluable tools for real time signal processing because of their significant advantages such as accuracy, reproducibility, and flexibility. Higher order digital filters are usually realized by cascading several second order/first order structures. The general second order digital filter transfer function contains two coefficients which are realized by fixed or finite length binary words due to practical limitations. This leads to inaccurate representation of the coefficients and results in errors in the realized transfer function. Several authors have evaluated the errors due to such inaccurate representation by studying the movement of poles of the realized second order digital transfer function. But such evaluation does not directly represent the sensitivity of the overall magnitude of the transfer function due to errors in representing the coefficient values. In this thesis, the fractional deviation in the overall magnitude of the transfer function is used as a figure of merit for the evaluation of various second order digital filter structures. Several digital filter structures described previously in the literature, some sampled data (switched capacitor) filters, and some new structures have been considered for such an evaluation. The evaluation is restricted to those structures which realize the coefficients using only two multipliers. The evaluation of fractional deviation involves computation of several sensitivities, some of which are structure independent and some structure dependent. Since these computations can be best carried out using a digital computer, a computer aided sensitivity analysis procedure has been developed and used to compare and evaluate various structures. Such an analysis can be applied to choose the “best” structure for realizing a given transfer function. Another important aspect in digital filter implementation is the evaluation of the effect of round off, invariably present during signal processing. Earlier methods of digital filter implementation used hardware multipliers and accumulators, which provided the flexibility to select a suitable word length to meet sensitivity specifications. However, the current technique for implementing digital filter structures uses digital signal processor (DSP) chips. This imposes a restriction of fixed word length for realizing the coefficients. Hence the round off noise is dependent on the DSP architecture. Thus, the systematic evaluation of round off noise involves identification of noise sources in each structure, evaluation of their transfer functions to the output, and evaluation of the overall round off noise due to all these various sources. In this thesis, the overall round off noise is used to compare the various digital filter structures considered earlier.