| dc.contributor.advisor | Rangaswamy, S V | |
| dc.contributor.author | Kodandapani, K L | |
| dc.date.accessioned | 2026-03-10T11:02:43Z | |
| dc.date.available | 2026-03-10T11:02:43Z | |
| dc.date.submitted | 1974 | |
| dc.identifier.uri | https://etd.iisc.ac.in/handle/2005/9115 | |
| dc.description.abstract | The thesis is concerncd v/ith a study of Recd-Mullor
Canonical (FMC) forms and the associated logic realizations.
Tv/o nonexhaustive procedures for obtaining minimal PS'IC forms
have been reviewed, One of them has boen modified to obta.in
improved upper bounds on the number of M C forms to be de rived for choosing the minimal ones. It has been shov/n
that the. task of obtaining minim8.1 R4C forms is further
simplified for some special types of switching functions.
Some alternatives to the R4C networks for reaJLizing sv/itching
functions that achieve a reduction in both the number of
levels and the number of gates have been proposed. A straight forv/ard factoring techniq.ue for obtaining multi-level AND-EOR
circuits has been suggested. A generalization of the HiC
forms to multi-valued logic has been obtained and several
results regarding the M C forms have been generalized to the
multi-valued case, A rectangular universal cellular array
based on the M C forms for realizing any sv/itching function
has been proposed. An algebraic generalization of the well known q-function array to multi-valued logic has been ob tained. The problem of fault diagnosis in R4C netv/orks and
multi-level AND-EOR realizations has been investigated. | |
| dc.language.iso | en_US | |
| dc.relation.ispartofseries | T01122 | |
| dc.rights | I grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation | |
| dc.subject | Minimal forms | |
| dc.subject | Multi-level circuit synthesis | |
| dc.subject | Multi-valued logic | |
| dc.title | Logic relizations based on reed-muller canonical forms Ph.D. Thesis | |
| dc.type | Thesis | |
| dc.degree.name | PhD | |
| dc.degree.level | Doctoral | |
| dc.degree.grantor | Indian Institute of Science | |
| dc.degree.discipline | Science | |