Design for Testability and fault analysis in PLAs and General combinational circuits

Abstract

Programmable Logic Arrays (PLAs) are being extensively used in today’s LSI (Large Scale Integration) and VLSI (Very Large Scale Integration) circuit design as flexible building blocks for implementing combinational logic functions. The primary objective of this thesis is the formulation of systematic procedures to render the fault diagnosis of PLAs highly reliable.

First, a test generation algorithm is developed to obtain a compact test set for the detection of all detectable single crosspoint faults in a PLA. Powerful heuristics are employed to speed up the computation of tests. Results of a Pascal implementation of the algorithm show that its performance is comparable to the best existing algorithms for PLA test generation and, in most cases, generates a more compact test set.

The limitations of single crosspoint test sets for PLAs, such as undetected crosspoint faults and inadequate multiple fault coverage, are examined. The need to design PLAs for improved testability is emphasised. A hardware approach is proposed for the design of testable PLAs, which incorporates a shift?register and an additional observable output line called a watch?line as extra hardware. This method greatly simplifies test generation for PLAs and produces a test set with 100?% multiple fault coverage of all crosspoint, stuck, as well as bridging faults in a PLA, while requiring significantly less additional hardware and considerably fewer test vectors compared to other similar approaches.

Another objective of this thesis is the analysis of the multiple stuck?fault detection capability of single stuck?fault test sets in general multiple?output combinational circuits. The theoretical analysis of “Guaranteed To Be Detected (GTBD)” faults in a circuit reveals that irrespective of circuit structure, the fraction of GTBD faults rises exponentially with increasing fault multiplicity. It is shown that more than 99.6?% of all multiple stuck faults in any circuit having three or more observable outputs is guaranteed to be detected by a single fault test set (SFT) that is capable of detecting stuck faults on the primary output lines. Such results provide a theoretical justification for the popular view that high fault coverage against small fault multiplicities is both necessary and sufficient to detect all multiple stuck faults of interest in a combinational circuit.