Scalable Solutions for Advancing the Performance and Reliability of 2D Transition Metal Dichalcogenides (TMDs)-Based Nanoelectronic Devices

Abstract

The semiconductor device technology has evolved through the years by scaling down the device dimensions and changing device architecture to improve speed, power dissipation, packing density, and overall performance. To mitigate the problem of short channel effects (SCE) due to scaling in planar field-effect transistors (FETs) and improve the electrostatic control on the device’s channel, the FinFET architecture was first used in 2011. To further scale down the device dimensions and keep Moore’s law alive, Gate-All-Around (GAA) architecture is currently being used for sub-3 nm technology node. To continue this scaling further, the Complementary FET (CFET) architecture is currently under research, and according to the IRDS roadmap, its commercial application is expected to begin after 2028.

When the channel length of the devices is scaled down, to reduce the SCE, along with the change in the architecture for better electrostatic control, the channel thickness should also be scaled down accordingly. However, in the case of silicon (Si), carrier mobility is found to degrade drastically when its thickness is reduced to less than 3 nm. Therefore, for the sub-1 nm technology node, where the channel thickness will need to be scaled down significantly along with the change in the device architectures for high electrostatic control, Si cannot be used as the device’s channel. To solve this issue, the IRDS roadmap projects a new class of materials known as two-dimensional (2D) materials with a very high surface-to-volume ratio. Transition metal dichalcogenides (TMDs) like MoS2, WS2, MoSe2, and WSe2 are a group of 2D materials that have sub-1 nm thickness, high surface-to-volume ratio, tunable bandgap, appreciable mobility in ultra-low thickness regime, and flexibility. These properties of TMDs make them a promising candidate for the sub-1 nm technology node. Among these TMDs, MoS2 and WSe2 show the most favorable characteristics for NMOS and PMOS devices.

However, several bottlenecks exist that need to be solved before the TMDs-based devices can be used commercially. For example, MoS2-based FETs show a high contact resistance due to the Schottky nature of metal/semiconductor contact, degrading the drive current and speed of circuits based on them. Also, MoS2 has intrinsic defects like sulfur vacancies, which lead to the emergence of traps in the channel and deteriorate the carrier mobility. Further, MoS2-based FETs intrinsically show n-type conduction and have a depletion-mode (D mode) characteristic, causing a high OFF-current (IOFF) at zero gate bias, which leads to significant static power dissipation when used for CMOS circuits. Also, since TMDs like MoS2 and WS2 have a high surface-to-volume ratio, they are prone to easier changes in their characteristics due to ambient adsorptions, like oxidation, trap state formation, and alteration in carrier concentration due to charge transfer doping. These issues lead to degradation in the performance and reliability of devices and circuits based on them. Therefore, this work focuses on providing industrially compatible and scalable solutions to these issues to empower the commercial usability of TMD-based devices.

This work first deals with providing an effective methodology to reduce the contact resistance and passivate the intrinsic sulfur vacancy defects in MoS2-based FETs. To achieve this, fluorine ions are implanted in the source/drain contact regions of MoS2 FETs using CF4 plasma, followed by their cyclic field-assisted activation. Experimental analysis and density functional theory (DFT) simulations revealed that fluorine ions migrate from the source/drain contact regions into the MoS2 channel and bond to sulfur vacancies, resulting in simultaneous passivation of defect sites and introduction of n-type doping in the channel. This dual action effectively narrowed the Schottky barrier width at the metal/semiconductor contact, yielding ~90% reduction in contact resistance and ~150% boost in field-effect mobility. As a result, the ON-current (ION) of exfoliated and CVD-grown MoS2 FETs improved by ~90% and ~480%, respectively, with a high ION/IOFF ratio of 7 to 8 orders.

Following that, this work addresses the lack of p-type doping in MoS2 and the prevalence of intrinsic depletion-mode (D-mode) characteristics in MoS2 FETs, which leads to high static power dissipation and limited logic functionality when used for CMOS circuits. To solve this issue, the MoS2 is exposed to the argon plasma to remove the sulfur atoms from the top of the MoS2 surface and create sulfur vacancy sites, followed by an O2 bath to chemisorb oxygen at those sites. It results in the formation of shallow acceptor states near the valence band of MoS2, thereby enabling controlled p-type doping. This method successfully transformed the intrinsic D-mode characteristics of MoS2 FETs into enhancement-mode (E-mode), with IOFF in the tens of picoamperes (at zero gate bias) and an ION/IOFF ratio of more than seven orders (at zero gate bias). Additionally, by removing the sulfur atoms, this technique significantly reduced the contact resistance in the p-doped E-mode devices by increasing the orbital interaction between metal and Mo atoms, enabling the fabrication of high-performance top-gated E-mode MoS2 FETs and NMOS inverter circuits with E-mode driver FET. These results demonstrate clear viability for complementary CMOS logic integration using TMD materials.

After dealing with issues of high contact resistance and lack of p-type doping in MoS2, this work presents the reliability and performance limitation issues, such as high contact resistance in WS2-based FETs and photodetectors. To solve these problems, this work demonstrates an industrially acceptable and scalable dual layer passivation technique, where the e-beam-evaporated Al2O3 is used as the first passivation layer, which induces significant n-type doping in WS2. This n-type doping assisted in shielding the electrons in the WS2 channel from Coulomb impurities and narrowing the Schottky barrier width at the metal/semiconductor junction, thereby improving the carrier mobility and contact resistance, respectively. A subsequent passivation using more uniform and crystalline atomic layer deposition (ALD)-deposited Al2O3 layer provided robust environmental encapsulation, effectively preventing ambient adsorption over prolonged ambient exposure and boosting the reliability of WS2-based devices. This technique delivered an improvement of ~108% and ~800% in field-effect mobility and contact resistance of WS2 FETs, respectively, which led to an enhancement in their ION and ION/IOFF ratio of ~700% and ~2 orders, respectively. Further, this technique resulted in a 178-fold boost in the photocurrent and responsivity of the WS2-based photodetector. Further, long-term stress tests under the ambient conditions confirmed minimal performance degradation in dual-layer-passivated WS2 FETs, proving this method’s practicality for enhancing the reliability of WS2-based devices.

Since the inverter is the fundamental element of various logic circuits, this work further specifies and discusses the reliability issues in MoS2-based NMOS inverter under various practical stress conditions representative of real-world circuit operation, like, repeated input voltage sweeps across logic-level thresholds, high-frequency input pulses at the gate node, and prolonged biasing at logic 0/1 states for hundreds of seconds. Monitoring shifts in output high voltage (VOH), output low voltage (VOL), voltage gain, rise/fall times, and dynamic switching characteristics from the voltage transfer characteristics and transient response measurements, further accompanied by Raman and PL spectra, revealed performance degradation causes and their mechanisms in MoS2-based NMOS inverter circuit. For all the stress scenarios, the charge trapping at the MoS2/dielectric interface of driver/load FET and changes in doping, strain, and material quality of MoS2 are identified as the key contributors to NMOS inverter performance degradation. Further, the usage of hexagonal boron nitride (hBN) as the gate dielectric was found to effectively mitigate these issues by providing a trap-free MoS2/dielectric interface, significantly improving both static and dynamic reliability metrics. Therefore, this study offers an in-depth understanding of the reliability issues in MoS2-based inverter circuits, their causes, and potential solutions.