| dc.description.abstract | In this work, a detailed study of the properties of B-Splines that are useful for efficient evaluation has been conducted. Using these properties, a few VLSI architectures have been proposed. The following are the contributions of this thesis:
A highly parallel systolic architecture has been proposed for the computation of uniform B-Spline curves.
A composite architecture for the evaluation of uniform rational and non-rational B-Spline curves and surfaces has been developed.
An algorithm for the computation of B-Spline basis functions has been highlighted.
Using the above algorithm, a systolic architecture for the generation of basis functions is presented.
Finally, using the above basis function evaluation architecture, a unified architecture to compute uniform/non-uniform rational and non-rational B-Spline curves and surfaces has been presented as the final solution to the problem addressed in this thesis.
A performance comparison of the above unified architecture has been done, and the comparison with architectures presented in the literature shows its superiority over other implementations.
6.1 Future Work
The architecture developed in this thesis for the generation of NURBS surfaces can be integrated into a graphics pipeline, as shown in Figure 11, before the transformation stage. The command processor, which interprets graphics commands, assigns the task of calculating the NURBS curves and surfaces to this architecture upon receiving such a command. Other commands are transferred directly to the pipeline, bypassing this architecture.
This NURBS architecture generates points on the surface, curve by curve, for various values of uuu. These values must be accumulated and combined with the next curve to form triangular patches. These patches, along with their vertex normals, are sent to the pipeline for rendering.
An interface between the NURBS architecture and the pipeline to perform this accumulation and tessellation of the surface needs to be developed. An additional interface between the command processor and this architecture for collecting data such as control points, weights, knot vectors, and parametric ranges also needs to be developed. These developments will be meaningful only when targeted at a specific workstation architecture. Moreover, the active support and collaboration of a workstation manufacturer is essential for the success of such developments.
The motivation for this thesis is the need for parallelism and better solutions to problems in geometric modeling applications. This work focused on the faster generation of models using B-Splines. Rendering these models is the next logical step. Hence, this work can be extended to explore parallel algorithms and special-purpose architectures for rendering B-Spline patches.
Apart from special-purpose architectural solutions, parallelization of the computation, rendering, and display of B-Splines can also be done on general-purpose architectures. The data distribution aspect of this problem in shared-memory tightly coupled systems provides a rich source of research problems. Furthermore, in a network of machines where computation is distributed and display occurs on a single machine, the display often fails to keep up with the speed of computation due to the network bottleneck between computing and display machines. Future work can focus on developing better interconnection networks to address this issue.
This thesis, which has solved a major problem in modern modeling systems, opens up a large area in the field of graphics and geometric modeling for further research. | |
