DPLL's for network synchronization: a new approach.

Abstract

A new DPLL has been described in this thesis to overcome some of the limitations of the conventional second-order DPLL in the context of network synchronization applications. The analytical and computer simulation studies have shown a reduction in the acquisition time and the avoidance of cycle slips during acquisition. This has also been verified experimentally in the laboratory by realizing the new DPLL using state-of-the-art ICs and a 65C02 µP kit. Important observations and significant results of these investigations are given below:

(a) Analytical and Computer Simulation Studies Equations have been derived for the phase error, the convergence, and the stability criteria of the new DPLL using the fixed-point and contractive mapping theorems. Tables 3.3 and Appendix III present the simulation study of this DPLL together with that of the conventional second-order DPLL. Table 3.5 gives a comparison of both these DPLLs for different frequency offsets and initial phase error conditions. The following conclusions now emerge from these studies:

For the new DPLL, there is a reduction in the number of acquisition steps, and therefore in the acquisition time (tact_{ac}tac?). The new DPLL acquires frequency and phase lock for all the initial phase error conditions, with the avoidance of cycle slips.

From the analytical study in Section 3.3.4, it is also clear that the tracking performance of the new DPLL is similar to that of the conventional second-order DPLL, viz.:

It has narrowband noise rejection and phase jitter suppression properties; and It has frequency memory which makes it tolerant to signal fadeouts.

(b) Experimental Verification In order to verify the results of the analytical and computer simulation studies, experiments have been conducted in the laboratory for both the new and the conventional DPLLs. To cross-check the measurements, two methods have been used, viz.:

Using a storage CRO; and A lock indication circuit.

A cycle slip detector has also been developed to indicate the number of cycle slips in the acquisition process. The results are summarized in Tables 4.3-4.5, which clearly show the reduction in tgt_gtg? and the avoidance of cycle slips. Although the experimental work has been carried out for a DPLL center frequency of 40 Hz for convenience of experimentation, they are demonstrative of the usefulness of the new DPLL operation at any other frequency. However, for realizing the new DPLL for operation in the MHz range (which is a common requirement in network synchronization), it is necessary to either make use of hardwired logic/ASIC approach or 16-bit CPUs with a higher operating speed. It is clear from this discussion that the new DPLL is a useful building block of modern telecommunication systems. Considering the present trends in IC technology, it is possible to realize the new DPLL in ASIC form using one or the other of the approaches discussed in Chapter 2. This is expected to increase the popularity of these DPLLs.