Design,fabrication and instrumentation of a broadcast bus multicomputer system

Abstract

In this thesis, we propose, design, and give the implementation details of a Multicomputer System called the Broadcast Bus Multicomputer System (BBMS). We also model the message broadcast bus and compare the analytical results with the measured results of the implemented system. The BBMS is being used as a testbed for experimenting with novel multicomputer algorithms, tasking mechanisms, granularity effects, etc. It is also being used as a hardware testbed to study communication patterns, bus arbitration schemes, bus characteristics, and other parameters of interest. The BBMS consists of a general-purpose frontend computer system that caters to all the programming requirements of the user and a backend consisting of the Computing Elements (CEs) interconnected with each other and the host through the Message Broadcast Bus (MBB). This thesis discusses the design and implementation of the MBB in detail. The MBB multicomputer system supports a parallel programming environment in the form of library support in the conventional MS-DOS operating system and Turbo-C language. The MBB features dual high-speed asynchronous buses, each with a 32-bit data path, a starvation-free bus access mechanism, and concurrent usage of the buses for exclusive message transfer. The communication controller of the MBB consists of two sub-modules — the transmitter and the receiver of messages. These sub-modules have been designed using high-speed FIFO buffers. The controller supports the selective reception of pattern-based broadcast message packets. This is done using an on-the-fly hardware-based pattern matching logic. The MBB has been designed to support instrumentation probes for non-invasive monitoring of the activity at various critical points of the bus. Supportive instrumentation logic for communication pattern measurements, timings, communication error rates, arbitration performance, etc., has been designed and built.