On the optimization of control memory and data paths in the design of microprogrammed computers and microprocessors

Abstract

In a microprogrammed processor, the size of the control memory depends upon the microinstruction word length (width of the control memory). An optimal microinstruction format reduces the width and hence the size of the control memory to the extent that parallelism in microoperations is not lost. The registers and functional units controlled by the microcommands are connected through interconnection buses. The number of interfaces such as drivers and receivers through which they are connected to the buses depends upon the data path organization. An optimal data path organization requires minimum interfaces without losing parallelism in data transfers. Parallelism in microoperations and data transfers is an essential requirement to increase the execution speed of the processor. Since the LSI chip area and the cost of the system depend on the size of the control memory and the number of interfaces in the data path organization, the optimization of both the factors becomes important. While the width optimization (referred to as bit optimization) of control memory is so far handled mostly in the switching theoretic approach, the data path assignment problem is handled either in a heuristic manner or in the dynamic programming method. This thesis deals with the bit optimization problem using the technique of bit steering applied to the mutually exclusive (in time) sets of microcommands obtained through the switching theoretic approach. The concurrency of microcommands in two mutually exclusive sets is expressed in the form of a matrix called concurrency matrix. The detection of microcommands that are bit steerable and their encoding is done with the help of the concurrency matrices. The technique enhances the extent of minimization of the control memory width over what is achieved in the switching theoretic method. The data path assignment problem is handled with the techniques of switching theory. The concept of bus compatibility for the data transfers is used to obtain the various ways of interconnecting the circuit modules with minimum number of buses that allow concurrent data transfers. These being the feasible solutions of the problem, the minimal interface solutions are obtained by assigning weights to the bus compatible sets present in the feasible solutions. This method is easier to implement and also takes less computation time than the heuristic or dynamic programming method.