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dc.contributor.advisorPriti, Shankar
dc.contributor.authorSrikant, Y N
dc.date.accessioned2025-10-07T10:52:04Z
dc.date.available2025-10-07T10:52:04Z
dc.date.submitted1986
dc.identifier.urihttps://etd.iisc.ac.in/handle/2005/7157
dc.description.abstractThis thesis explores the design of parallel algorithms for the compilation process, using a SIMD (Single Instruction, Multiple Data) shared memory architecture that avoids read/write conflicts. Several phases of compilation are studied, and efficient parallel algorithms are proposed for: Converting arithmetic infix expressions into syntax trees Restructuring expressions for parallel evaluation Generating code for SIMD machines from syntax trees Parsing a subclass of regular languages (PF(k) parsable languages) Parsing a subclass of deterministic context-free languages using a new hierarchical specification scheme Complexity analysis shows that most algorithms achieve a time complexity of O(log² n) using O(n) processors, where n is the length of the input string. An exception is the code generation algorithm, which requires O(n) time. These results demonstrate the feasibility and efficiency of parallel compilation techniques on SIMD architectures.
dc.language.isoen_US
dc.relation.ispartofseriesT02357
dc.rightsI grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation
dc.subjectSIMD Architecture
dc.subjectSyntax Tree Generation
dc.subjectParallel Algorithms
dc.titleParallel algorithms for compilation.
dc.typeThesis
dc.degree.levelPhD
dc.degree.levelDoctoral
dc.degree.grantorIndian Institute of Science
dc.degree.disciplineEngineering


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