Inkjet-printed transistors and circuits with two-dimensional semiconductors

Abstract

The escalating demand for wearables and large-area electronics has intensified the critical need for identifying novel semiconductor materials and technologies. While organic semiconductors offer flexibility and processability at lower temperatures, their transport properties reflected by the achievable carrier mobility and atmospheric stability are generally limited. The other explored material class - oxide semiconductors, is limited by their high processing temperatures. In contrast, inorganic two-dimensional (2D) materials exhibit properties conducive to the next generation of large-area and flexible devices, including appropriate band gaps, intrinsic flexibility, and the availability of both n-type and p-type semiconductors. Various techniques have been studied in the past for the large-scale synthesis of 2D materials, where the chemical and physical vapor deposition impose substrate limitations due to their high temperature requirement. Conversely, solution-based techniques provide substrate flexibility by operating at lower temperatures and obviate the need for high vacuum systems. When integrated with printing, solution-based techniques can allow roll-to-roll processing of inexpensive electronic devices through which disposable electronics can be realized. Owing to the advantages mentioned above, several research groups have fabricated transistors with solution-processed two-dimensional semiconductors. The literature reports in this domain demonstrate network transistors fabricated with semiconductors from Group-VI transition metal dichalcogenides (TMDs), such as MoS₂, WS₂, MoSe₂, etc. However, in a solution-processed film, there are networks of flakes, and the transport of charge carriers takes place through a lot of flakes and the respective inter-flake junctions. These inter-flake junctions introduce many non-tunable resistors and, as a result, control the overall electrical properties of the as-cast film. Due to this reason, it is difficult to take advantage of the intrinsic properties of solution-processed 2D semiconductors, which is often demonstrated with devices fabricated on a single flake. As a result, the attempts to fabricate transistors with solution-processing of 2D flakes turn out to be substantially inferior compared to those of the devices built on single flake of 2D TMDs. In the initial reports that demonstrated solution-processed transistors made of two-dimensional semiconductors, thick semiconductor layers have typically been used in order to overcome the high inter-flake resistance. However, the thicker semiconductor layer leads to poor gate control over the semiconductor film, resulting in a much reduced On-Off ratio. Later, attempts have been made to reduce the number of junctions by the use of larger flakes. The larger flakes resulted in better transistor performance, but the large lateral size of the flakes limits their fabrication possibilities with digital printing techniques, such as inkjet printing. Along this direction, later another attempt has also been made, where the flakes are covalently bonded to each other through diothiolated conjugated molecules. These improve the percolation pathway for the flakes; however, the improvement in transistor performance has not been substantial. In this regard, this thesis addresses the above-mentioned bottleneck of junction resistance by presenting several methods to achieve high-performance 2D transistors and circuits. Firstly, an innovative device geometry has been proposed to transform the conduction to the vertical dimension of the film, which is several tens of nanometers in thickness, as opposed to lateral conduction, where the channel lengths would be of the order of several tens of micrometers. As a result, the transport is now not limited by the inter-flake junctions; instead, the evidence for predominant intra-flake transport has been observed. At the next step, high-performance n-type transistors with printable 2D MoS₂ nanosheets have been fabricated, where the 2D MoS₂ sheets are exfoliated using multiple exfoliation techniques. The MoS₂ transistors fabricated using this geometry and using a composite solid polymer electrolyte (CSPE) as the electrolytic insulator have demonstrated high reproducibility with a current density of 300 μA μm^-1 and an On-Off ratio of 10⁷. Exploiting these high-performance transistors, depletion load type unipolar inverters and several logic gates, such as NAND, NOR, AND, and OR etc. are then demonstrated. The respective DC and AC performance has been analyzed. A maximum signal gain of 31 is demonstrated at a supply voltage of 1.5 V, and all the other circuits are shown to operate at 1 kHz. In the next section, high-performance p-type transistors based on printed tellurium nanowires and tellurene nanoflakes are demonstrated where an identical device geometry has been used. Then, the n-type MOS₂ and p-type tellurium transistors are combined to fabricate CMOS inverters. In the next chapter, an attempt has been made to print high-performance 2D TMD based transistors with traditional, lateral and long-channel transistor geometry. In order to lower the inter-flake resistance, major doping of the MoS₂ single-crystal has been used to push the Fermi level upwards, which resulted in a decrease in the work function from 4.5 eV to 3.3 eV. This also reduced the junction resistance substantially. Consequently, transistors even with lateral channel lengths as high as 150 μm could have been demonstrated. In fact, heavy doping induced metallic temperature dependent transport behavior. However, the heavy doping or the metallic nature of the MoS₂ flakes has not increased the off current of the transistors, and we observe a high On-Off ratio of 10⁷. This is because the large capacitance of the electrolytic insulator can induce strong band bending even at zero gate bias and completely deplete semiconductor channel which is even moderate to heavily doped. Moreover, a high current density of 280 μA μm^-1 has also been observed at the same time. Owing to such large channel length compatibility, fully-printed MoS₂ transistors with printed Mxene-based drive electrodes have been realized on photo-paper substrate. The devices are fully printed and cured at room temperature and demonstrate narrow level of performance variability. In summary, in this work, the importance of junction resistance on the transistor properties of solution-processed 2D semiconductors are examined and elaborated. Along the way, multiple solutions have been provided to overcome the bottleneck associated with inter-flake junction resistance and various high-performance transistor technology using different 2D semiconductors have been demonstrated.