ESD Design for Advanced CMOS and Analog nodes

Abstract

The study of Electrostatic Discharge (ESD) reliability within Integrated Circuits (IC) is crucial due to its direct influence on electronic device performance, longevity, and functionality. As semiconductor technology undergoes aggressive scaling, ESD design requirements become more stringent, and relying on past design concepts proves inadequate, potentially leading to unprecedented failures. This research combines experimental findings with Technology Computer-Aided Design (TCAD) to gain detailed physical insights into ESD protection device dynamics. Subsequently, device design guidelines are formulated for diverse technology nodes and applications. This work can be broadly classified into the following two threads: In the first segment, ESD challenges in advanced CMOS nodes are explored, particularly focusing on Fin-based Silicon Controlled Rectifiers (SCRs). Detailed 2D and 3D TCAD simulations reveal that non-uniform current distribution across fins severely limits the failure threshold. To overcome this limitation, a novel multi-finger variant of Fin-based SCRs is proposed, ensuring uniform current distribution and ideal failure current scaling. A detailed investigation into the current filament dynamics in Fin-based SCR devices was also conducted. With technology scaling below 180nm, capacitance loading of the ESD component on the I/Os starts increasing. To address this, a novel schematic was designed to achieve up to a five-order reduction in the device’s effective capacitance. In the second segment of this research, an exhaustive examination of the dynamics of ESD protection devices employed in analog technology applications is undertaken to develop reliability-aware ESD design guidelines. Lightly doped drains (LDD) have been known to cause sudden device failure upon triggering. Historically, this sudden failure has been attributed to weaker bipolar strength resulting from a degraded emitter junction with the introduction of LDD. A 5V ggNMOS with LDD, which was found to fail on the trigger, was investigated using detailed TCAD simulations. Physical insights into its filament dynamics were developed as a function of LDD placement using TCAD simulations. It was found that these devices were failing similarly to LDMOS devices after filament formation and the onset of space charge modulation, which was previously unknown. Based on this new understanding, design guidelines to mitigate failure on the trigger in ggNMOS devices were proposed and experimentally demonstrated. Furthermore, a gate bias-related weakness was identified under very fast Transmission Line Pulsing (vf-TLP) conditions. The surface depletion effect occurring at higher gate biases was found to be causing non-uniform finger turn-on and filament formation. The presence of LDD further increased the difficulty in achieving uniform turn-on. High-voltage ESD protection devices used in analog technology nodes were also studied in this work. LDMOS devices are conventionally prone to early failure on ESD strike due to current filament formation that triggers after space charge modulation. To mitigate such a failure and have a self-protecting concept, LDMOS-SCR, a p+ anode diffusion is placed in the N-Well of these devices to form an SCR path that protects the device under ESD strike. However, these devices are reported to suffer from severe power scalability issues, where, as the ESD pulse width increases, the failure current collapses. Detailed physical insights into the power scalability issues in LDMOS-SCR devices were developed. Based on these new insights, device design guidelines to address power scalability issues in LDMOS-SCR devices were developed and experimentally verified. Finally, a 40V LDMOS-SCR device with record-high on-current was developed. Based on the investigations into the device using TCAD, device design guidelines were developed.