| dc.description.abstract | Multilevel inverters (MLIs) are preferred for high and medium power applications due to their numerous advantages over traditional two-level inverters. MLIs generate output phase voltages with multiple levels, mitigating large dv/dt in phase voltages, which reduces electromagnetic interference (EMI) and alleviates stress on motor winding insulation. They distribute the DC bus voltage across multiple levels, lowering voltage stress on power semiconductor devices, allowing higher switching frequencies and reduced switching losses. This leads to improved harmonic performance (%THD) without bulky passive filters. MLIs can use low-voltage devices, making them cost-effective for high voltage applications and well-suited for industrial drives, electric traction, and power transmission systems due to their low distortion in phase voltages, decreased harmonic losses, and reduced torque ripple.
Basic MLI topologies include the Three-level neutral point clamped (NPC), Three-level flying capacitor (FC), and Three-level cascaded H-bridge (CHB) inverters, each with distinct advantages and challenges. For instance, the NPC inverter requires additional clamping diodes and isolated DC sources, while the FC inverter uses a single DC source with floating capacitors for additional levels, increasing complexity with more levels. The CHB inverter needs multiple isolated power supplies per phase. To address these drawbacks, hybrid topologies and new classes like stacked MLIs have been proposed. Variants such as active neutral point clamped (ANPC) and nested neutral point clamped configurations, along with three-phase open-end winding motors with dual-fed inverters, are also explored.
A key limitation of MLIs is their linear modulation range (LMR). Traditional Pulse Width Modulation (PWM) techniques like Sine-triangle PWM (SPWM) and Space Vector PWM (SVPWM) limit the LMR to the circle of radius 0.866Vdc in a hexagonal space vector structure. Beyond this, in the overmodulation region, significant lower-order harmonics are introduced, complicating linear speed control.
This thesis presents three novel MLI topologies. The first integrates a two-level inverter with capacitor-fed H-bridge circuits, extending the linear modulation range and eliminating low-order harmonics, beneficial for Electric Vehicle (EV) applications in the flux weakening region. The second is a four-level converter with a cascaded H-bridge (CHB) structure using series-connected capacitors from a single DC source, maintaining balanced voltages and expanding operational range. The third topology is for open-end induction motors with a seven-level space vector structure (SVS), featuring precise capacitor voltage regulation and extended modulation range without lower-order harmonics.
Experimental validation uses a 3 kW, 50 Hz, 415 V, 3-phase induction motor with a TMS320F28379D Digital Signal Processor (DSP) and a Xilinx SPARTAN-3 XC3S400 FPGA for control and PWM pulse generation. The proposed inverters offer significant advantages like a single DC power supply, extended linear modulation range, reduced dv/dt stresses, and inherent capacitor balancing, making them ideal for electric vehicles, medium voltage, and high-power motor drives. | en_US |
