Energy-efficient Hardware and Algorithmic Techniques for Design of Low-power Intelligent Systems

Abstract

Low-power design techniques involving hardware and algorithms framework are a fundamental challenge of the modern electronic system. The internet connects devices (IoTs) with advanced capabilities in sensing and processing the data proliferated in every domain of technology adoption. Wireless IoT devices have become the backbone of the digital ecosystem, from wearable watches and intelligent health monitoring devices to earphones shaping our daily lives. The portability of electronic devices relies on the power budget it uses to operate. The low-power design techniques for electronic devices have recently received significant attention. This thesis addresses low-power design challenges, focusing on hardware and software optimization to provide low-power solutions. The first problem addressed is the design of an ultra-low-power wake-up receiver front-end with an RO-VCO combination as the mixer stage of the intermediate frequency down-conversion of the receiver front end. The novel method of the receiver front-end wake-up module is designed. This design minimizes the active power of the receiver front while optimizing noise figure and gain; it receives a gain of 14.9 dB while consuming 75 µW from a 0.75 V supply. The low noise amplifier (LNA) is designed for the LNA with an increase of 16 dB with a noise figure of 5.7 dB and input third order intercept point (IIP3) of 18.16 dBm. In the second part of the thesis, a biomedical system’s portability depends upon the medical equipment’s power and size. The size of the equipment and power budget hinders access to healthcare support in the most remote part of the world. A novel algorithmic framework for portable ultrasound imaging systems based on deep generative learning and compressed sensing has been developed. Advancement in deep learning algorithms has shown application in signal compression via gradient-based learning. One such model variation auto-encoder is designed to learn the compressed pre-beamformed RF signal representation. This method demonstrated a significant improvement in power signal noise ratio (PSNR) and mean square error (MSE) compared to the state-of-the-art techniques. The third part presents an intelligent mechanism for audio processing based on deep learning. A single-speaker separation from the mixture of a speaker based on convolutional neural network auto-encoders is presented. The fourth contribution is developing a low-power signal conditioner, which is essential to provide various high-precision applications. The novelty of the design offers a low-power miniaturized solution that can directly interface with the processor, providing a solution for high-precision applications in industrial/medical systems. The ASIC has been implemented in 180 nm technology, consumed 285 µW of power, and takes an area of 1 mm2.