Fast Methods for Modelling and Simulation of Fully Integrated Voltage Regulators in Microprocessors
Fully Integrated Voltage Regulators (FIVR) have been introduced in the latest generation of high-performance server microprocessors to improve the performance and power efficiency of the processors. FIVR is a switched inductor DC-to-DC step-down converter with on-chip power bridges, control circuits and on-chip Metal-Insulator-Metal (MIM) capacitors. The inductors for FIVR are designed on the package using package traces and Plated Through Hole vias (PTH). Each FIVR module generates the voltage needed for the functional units such as the CPU cores locally, and a typical microprocessor package has more than 100 such FIVR modules. The switching frequency of FIVR is kept high (~100 MHz) to minimize the inductor size. The different components of FIVR are modelled and simulated using circuit simulators to predict the output voltage, input voltage noise, switching ripple, efficiency, etc., Due to the multiscale nature of FIVR, a lot of challenges are faced in the modelling and simulation of FIVRs by the circuit simulation approach. This thesis discusses the various challenges involved in the modelling and simulation of FIVRs and proposes fast methods to solve these challenges. At the high switching frequency of FIVR distributed effects dominate, and Full Wave Electromagnetic Extraction tools need to be used for extracting the models of the package inductors. Volume-based electromagnetic modelling tools such as the Finite Element Method (FEM) or the Finite Difference Time Domain (FDTD) method need more runtime to model the FIVR inductors as the entire volume needs to be meshed. The latest generation of FIVR inductors uses Magnetic materials for the magnetic cores with frequency-dependent permeability which further increases the runtime in volume-based methods. In this thesis, the fast surface integral equation method also known as the Method of Moments (MoM) is developed for modelling Perfect Electric Conductor (PEC) and PEC-dielectric/magnetic objects. The multiple FIVR modules in the chip share a common input supply (Vccin) for cost reduction. However, the sharing of the input supply also introduces the problem of noise coupling between the FIVRs. The load current transients at the output of one FIVR can couple to the output of other FIVRs through the input network. This noise is referred to as the Vccin feedthrough noise. The modelling of noise coupling between multi-domain FIVR is a challenge, and one normally runs into long run times or convergence issues in circuit simulation. In this thesis, two fast methods are developed to model and simulate the noise coupling in multi-domain FIVRs. The first method is a frequency-domain method and is based on the g-parameter transfer functions of FIVR. The second method is a time-domain method and is based on the state-space models of FIVR inductors and MIM capacitors determined from the Vector-Fitting technique. The proposed methods are demonstrated to improve the runtime and simplify the modelling of multi-domain FIVRs. The modelling of the input ripple noise due to the switching of the FIVR power trains is a challenge for multi-domain FIVR due to the need to include switching models of many FIVRs in circuit simulation. The input power supply (Vccin) is also a large, distributed network that prohibits the detailed switching simulation of multi-domain FIVRs. Convergence issues are faced in circuit simulations with such large models and the runtime is high. In this thesis, a Harmonic Domain (HD) method based on Linear Periodic Theory is developed to model the switching ripple voltage in multi-domain FIVRs. The various challenges faced in the circuit simulation approach can be avoided using the Harmonic Domain method. In FIVR domains with high load current, many FIVRs are ganged in parallel to supply the high load current. The modelling and simulation of ganged FIVR is a challenge due to the large scale of the problem with many FIVR modules ganged together with a large output power plane. The tuning of the FIVR control loop to attain the stability of ganged FIVRs remains a challenge with circuit simulation-based methods. Convergence issues are frequent in circuit simulations, and the runtime is high in circuit simulations. In this thesis, transfer functions are derived for ganged FIVRs from the extracted models of FIVR inductors and on-chip MIM capacitors. The transfer functions are used to model the stability of the ganged FIVR and can be used for the transient analysis also. The tuning of the FIVR control loop in a single domain FIVR is a challenge as there are a lot of Resistor-Capacitor (RC) combinations of the op-amp compensator circuit in the FIVR feedback control loop. The RC values need to be tuned to meet the control loop specifications such as the Unity Gain Bandwidth (UGB), Phase Margin (PM) and Gain Margin (GM). The practical op-amp compensator is non-ideal, and it is difficult to model its behaviour using analytical tuning methods such as the k-factor method. In this thesis, a machine learning method based on Bayesian Optimization is developed to tune the FIVR control loop and is demonstrated to reduce the number of circuit simulations significantly compared to traditional optimization methods. This method can be easily extended to post-Si measurements where the optimization is done on the fly and the next set of samples to be measured is selected based on the machine learning algorithm.