Investigations on Generation of Multilevel 24-Sided Polygonal Voltage Space Vector Structures Without Vector Averaging for Variable Speed Drives

Abstract

Induction motors are mainly powered by two-level inverters in low-voltage, low-power drive applications. For medium and high voltage applications, a conventional two-level inverter needs high voltage rated switches, operates at high switching frequency to get better voltage quality, and produces high dv/dt at switching instants. While operating at six-step mode for full speed operation, a conventional two-level inverter produces low-order harmonics, mainly 5th, 7th, 11th, 13th, 17th, 19th, and so on. These lower-order harmonics produce torque pulsations, which can damage the motor and affects produced torque and power. Conventionally these low order harmonics are suppressed or eliminated by employing bulky and costly passive filters, which degrades dynamic performance of the motor. Another technique based on modified pulse width modulation is selective harmonic elimination, which suppresses fundamental voltage along with harmonics resulting in underutilization of the DC-link voltage. Multi-level inverters are widely employed in high power and high voltage motor drive applications due to lower harmonic distortion and lower dv/dt in the phase voltage. However, multi-level inverters produce hexagonal space vector structure (SVS) and introduce lower-order harmonics in phase voltage during operat= ion in overmodulation region. Also, as the levels increases, number of switches, number of capacitors, diodes and isolated power supplies also increases. Polygonal SVS is a method for eliminating lower-order harmonics in full operating region. This thesis addresses the above-mentioned issues by generating a two-level and multi-level 24-sided polygonal SVS with real active vectors instead of switched average vectors. Each active vector is a real vector in contrast to switched average vectors in literature. The generation of real 24-sided vectors minimizes switching losses and improves the quality of phase voltage compared to switched averaged vectors technique. 24-sided polygonal SVS scheme eliminates lower order harmonics up to 19th order from motor phase voltage throughout the modulation range. The first work presents a method of generating 24-sided polygonal SVS comprised of 24 real active vectors and a zero vector. In the second work, a multilevel 24-sided polygonal SVS is presented, which suppresses higher order harmonics along with elimination of lower order harmonics from motor phase voltage. In the third work, an inverter circuit to generate a thirteen-level 24-sided polygonal SVS comprised of 288 real active vectors and a zero vector is presented. The SVS generated in third work is denser than the scheme pr= esented in the second work, which further improves output voltage quality, without altering the power circuit topology. In all above three works, vector timing computation is required, and reference vector is realized by time averaging nearest three vectors. To ensure the elimination of timing computation, a 24-sided polygon must be available for reference vector of any magnitude. In the fourth work, a variable speed induction motor drive to generate 24-stepped voltage waveform throughout modulation range is presented. Inverter circuit is realized using primary and secondary inverters feeding an open-end winding induction motor. Primary and secondary inverters are implemented by cascading two-level inverters. DC sources for both inverters are realized using a simple star-delta transformer combination. The presented concepts are verified with laboratory prototypes. The presented work is suitable for medium voltage and medium power induction motor drive applications.