Device-Circuit Reliability Co-Design in High voltage and Power devices

Abstract

For the last four decades, silicon CMOS technology has captured a significant share in IC, smart power IC, SoC, and the power device market. But there is aggressive research on other materials such as graphene & similar 2D materials and wideband gap materials. But, several aspects, including the fabrication process to improve device performance [7,9,12,13], understanding the device reliability physics [8,10,11], interconnection and packaging, need to be matured before these compound materials take the limelight. Besides these, a fab set-up for large scale production requires high NRE capital. On the other hand, Silicon had been through a great degree of maturity. Moreover, for intelligent power applications, Silicon has superior reliability. Therefore, Silicon is predicted to capture the power device market till the other materials gain perfection.

Besides the commercial market, the requirement for discrete and integrated power device technology within the strategic sector is enormous. Discrete power switching devices (often power MOS or IGBT switch) and power RF devices are used in numerous onboard power electronic and power RF applications. The first part of this work strives to bridge the device-circuit co-design gap that has severely limited predictive modelling of circuits for high power applications such as Radio Frequency Power Amplifiers (RF PAs) using high power devices LDMOSs and GaN HEMTs. A correlation between the device’s intrinsic parameters and PA performance is explored, and the iterative process aims to provide a high-performing circuit.

LDMOS is one of the prominent power devices which adopts CMOS processing and easy integration. The lateral double diffused MOSFET (LDMOS) is the predominant power device in implementing Power integrated circuits PICs because of its attractive electrical characteristics such as low on-resistance, high breakdown voltage, high input impedance and fast switching frequency. To obtain high breakdown voltage with low on-resistance for LDMOS, RESURF technology is used, in which the vertical p-n junction depletion layer between the n-type drift region and p-type epitaxial region and its interaction with lateral p-n junction depletion between the p-type channel and n-type drift region is optimised to reduce the surface electric field to obtain high breakdown voltage. A field plate (FP) on top of the gate and a drain field plate on top of the drift region is introduced to improve breakdown voltage further. These field plates help reduce feedback capacitance (Cgd) and increase the breakdown voltage FP LDMOS.

This work explores optimising the field plates for achieving breakdown characteristics above 900V without altering the on-resistance of the devices [2]. It covers major classical power devices from conventional design to non-conventional device designs. Conventional devices without field plates show 30% lower breakdown voltages than those with field plates. It can be concluded that field plates play a vital role in enhancing the breakdown characteristics of the device. Taking optimised design further, the field plates are introduced into non-conventional devices, where RESURF and SOI-based devices are explored. Along with the performance studies, the reliability of these structures is also explored. Regarding reliability, RESURF based devices show a higher tendency of deviation/degradation when stressed, up to 20% higher than the breakdown condition like that of the conventional devices without Fp. Further, the role of each field plate individually under the ESD condition is explored [3]. It was clearly understood that field plates at the source side play a significant role in distributing the junction electric field, while field relaxation at the drain side helps in improving the failure threshold. Gate and Source field plates improve the trigger voltage characteristics up to 54%, while drain field plate improves the failure threshold up to 60%.

Power semiconductor device industries are aggressively looking for system-on-chip (SOC) solutions for power amplifier (PA) circuits and are exploring different technologies, including gallium arsenide (GaAs), to more recent and intriguing gallium nitride (GaN) technologies, for power transistors with Radio Frequency (RF) applications. The advantage of silicon technology for RF applications lies mature fabrication process at low cost and their easy integration capability with the CMOS technology. Applications that require radio frequency power amplifiers such as broadcast, ISM (industrial, scientific, and medical), avionics, radar, wideband communications, telecom & satellite communications, RF heating applications, etc. Among them, the 50V RF LDMOS device is mainly used in wireless broadcast, ISM, and radar, which requires a higher breakdown voltage and power density. For 50V RF LDMOS with 0.35µm CMOS technology, the breakdown voltage must be higher than 100 V to guarantee a reliable operation. RESURF technology and the introduction of field plates have improved the breakdown voltage to 114V. Both DC and RF performance of various designs of FP RF LDMOS are evaluated, and results show that industry-leading performance is achieved [1]. Electrostatic Discharge (ESD) robustness was studied for the FP RF LDMOS designs as ESD has been identified as a source of damage to unprotected devices. Hot Carrier Injection (HCI) reliability was also investigated to address the complete reliability of these devices.

Though Silicon-based transistors have the advantage of mature technology, the requirement for high power and high-frequency devices demands transistors based on semiconductor materials with large breakdown voltage and high electron velocity. GaN is an attractive candidate for power amplifier applications because of several superior qualities in amplifier applications achieved due to its semiconductor properties. The wide bandgap in Gallium Nitride based transistors results in higher breakdown voltages because the ultimate breakdown field is the field required for band-to-band impact ionisation. Also, its high electron saturation velocities allow high-frequency operation. GaN can be used to fabricate high electron mobility transistors (HEMTs), which have high carrier concentration and higher electron mobility due to reduced ionised impurity scattering. A rigorous device-circuit co-design investigation of AlN/GaN HEMT to explore its feasibility for power amplifier operation at frequencies > 1THz. Both class A and class AB operations were invested. A novel device-circuit co-design methodology was adopted [4], which involves (i) device design optimisation using a well-calibrated TCAD setup, (ii) careful extraction of large-signal model cards with I-V, C-V & S-parameter matching, and finally (iii) source-load pull-based power amplifier design/exploration, for every device design investigated. For PA operation, both class A and class AB operations were invested while exploring PA gain, output power, efficiency at 1dB compression point, and linearity through dual-tone (IMD3) investigations. Besides, a complete range of device design parameters was investigated to explore the ultimate scalability limit and narrow down the device design window that can enable THz operation.

The last two decades have witnessed significant scaling in MOS technology from sub-micron to sub-nm level. To achieve devices with good performance at a small dimension, it was essential to explore new device architectures which could offer subthreshold swing (SS) values below 60 mV/dec. Several CMOS-like structures were designed, such as Fin-FETs, Nanowire Gate All Around (GAA) MOSFETs, Carbon nanotube FETs, Tunnel FETs, etc., which could lower the leakage current at small dimensions. Among these, TFET could achieve SS less than 60 mV/dec attributed to a fundamentally different mechanism for carrier injection. Hence, TFET is considered a future on the roadmap. A prediction of reliability is essential in choosing a device for a particular application. Therefore, it is necessary to understand the reliability of devices at the design stage itself. As technologies advance towards the deep submicron, the ESD (Electrostatic Discharge) protection design issues have become more critical. The second part of this work tries to understand the ESD robustness of a couple of novel Tunnel FET architectures.

A novel Fin-enabled vertical or area-scaled tunnelling FET is proposed for sub- 10-nm channel length operation. This device enables a smooth transition from FinFET technology to Fin-based vertical TFETs, while enjoying the benefits of FinFET architecture. To make this device commercial, it’s essential to understand the reliability performance of this device. This work explores the reliability physics of this device with detailed physical insight into the device’s operation and failure under ESD stress conditions [5]. The proposed device has a deep N+ implant underneath the P+ source, like adding a pocket between the source and gate for the ESD protection applications. Early avalanche assisted BTBT at the source-pocket junction, in addition to the drain-substrate junction, causes the device to turn on at lower voltages, lower self-heating resulting in improved failure current in the proposed device with less area overhead.