ESD Reliability Physics and Reliability Aware Design of Advanced High Voltage CMOS & Beyond CMOS Devices

Abstract

Electrostatic Discharge (ESD) reliability is one of the major reliability concerns in integrated circuits (IC), which if not addressed while designing devices and circuits, can lead to a permanent damage to the Integrated Circuits. The same becomes a rather more stringent in case of system level ESD events (System level ESD), which usually occurs in uncontrolled or harsh environments. To address these issues physical insights into the non-equilibrium electron-phonon (electro-thermal) behaviour of these devices, under nano-second time scale high-current conditions, are required to be developed. These insights are subsequently used to develop reliability aware device. Keeping this larger problem in mind, in this work, we focus on developing physical insights into ESD behaviour of advanced high voltage CMOS/BiCMOS & beyond CMOS device options. Using the physical insights developed, this work also demonstrates using computations and experiment’s reliability aware device design. The thesis/work is divided into following threads:

In the first part of this work, insights into various system level ESD problems in advanced High Voltage CMOS devices is developed. High voltage functionalities are the key for building system on chips (SoC) in mobile and automotive products. However, high voltage LDMOS/DeNMOS devices are prone to early ESD induced damages with charge modulation induced current _laments. To withstand extremely high current levels ( 30 A), during system level ESD events, in lowest possible area footprint, Silicon Controlled Rectifier (SCR) solutions are preferred. SCR can switch from a high voltage blocking state to an ohmic state and conduct high current levels. However, implementing SCR in High voltage LDMOS/DeNMOS technologies presents different challenges. First part of the thesis focuses on three of such major challenges i.e. Power scalability, Window failures when stressed through Common Mode Choke (CMC) and Air discharge failures. Furthermore, HBM and CDM qualified HV-SCR devices have found to cause early failures during system level stress conditions. System level discharges can last longer than HBM & CDM time scales (100ns), SCR should survive for pulse widths > 100ns. In this thesis, a unique low current ESD failures in LDMOS based SCRs during snapback is reported for the first time. Failure is universal to LDMOS-SCR devices designed as an efficient MOS switch and found to be specific to a window of current between trigger and holding state and can only be captured using high resistance load-line in Transmission Line Pulse (TLP) test system. This resulted in severe power scalability issues in LDMOS-SCRs for longer stress durations (Pulse width>100 ns). While using systematic experiments and 3D Technology Computer Aided Design (TCAD) simulations, we have developed detailed physical insights into the low current ESD failure phenomenon in LDMOS-SCR devices. Physical insights developed has resulted in design solutions to avoid low current failure and mitigate power scalability issue without interfering with functional operation and MOS performance. Further, the severity of the power scalability problem with increasing LDMOS voltage classes (from 40V Design to 80V LDMOS) is highlighted with a need for novel design strategies. A systematic design approach is presented to evaluate the effect of different design parameters on LDMOS _lament and SCR turn-on near the snapback region. New design guidelines are presented to improve the power scalability without compromising on its ON-state DC (functional) and Safe Operating Area (SOA) characteristics. On the other hand, signalling at certain high voltage I/Os can go below ground levels. Hence, Bidirectional SCR (BDSCR) protection elements are needed to block high voltage under different stress polarities. Power Scalability of High Voltage BDSCR for long duration pulse discharges (PW >100 ns), is also studied in this thesis. Power scalability trends are found to be sensitive to the Transmission Line Pulse (TLP) measurement set-up. Detailed physical insights into the early formation of current filaments along with filament motion in BDSCR is presented in detail using 3D TCAD. Dynamic current filament motion in Bi-directional high voltage SCRs is found. Back and forth current filament motion is found to improve the power scalability trends in BDSCR devices for long stress durations. Finally, impact of silicide blocking in mitigating filament strength has been studied, which in turn improves the ESD robustness and overall power scalability. The device design and physical understanding from investigations in helped to come-up with a new approach to engineer LDMOS drivers for safe snapback. Proposed method considers engineering both static filament & Dynamic/Moving current filaments in LDMOS design. Dynamic filament motion and its relation to NPN turn-on engineering is studied. A unique window failure in LDMOS near snap-back discussed for the first time in LDMOS designs. The presented approach resulted in 10-time improvement in ESD robustness for self-protecting concepts. Finally, different fundamental questions related to origin of filament motion are explored with the help of engineered LDMOS Designs. Another major challenge in development of HVSCR is, its survival against system level ESD stress through Common Mode Choke (CMC). Some of the communication pins (CAN) in automotive ICs need to pass system level IEC test through choke. CMC is an on-chip component present in ESD stress path. A unique failure mechanism for system level ESD stress through a CM choke is investigated. Presence of choke in stress path is found to change current waveform shape that ESD protection devices experience on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in Drain Extended NMOS SCRs (DeNMOS-SCR). 3D TCAD simulations are used to understand the device behaviour and failure under the peculiar two-pulse shaped IEC current waveform. A novel DeNMOS-SCR design is demonstrated to increases ESD robustness against the peculiar two pulse stimulus and to avoid system level ESD failures. Air discharge failure in HV-SCRs is another major bottleneck in developing on- chip system level protections. High voltage BDSCR devices are found to be vulnerable to system level air discharge failures. The failure observed is sporadic in nature and found to be function of pulse rise time. Root cause for such SCR failure sensitivity to specific rise times is studied in detail using Multi-Finger 3D TCAD Simulations. A novel design solution is prosed to improve BDSCR robustness against the air discharge failures.

Second part of the thesis focuses on understanding ESD device physics of new transistor concepts such as Tunnel FETs and graphene-based FETs. Current as well as the time evolution of the junction breakdown, device turn-ON, voltage snapback, and finally the failure mechanism is studied using both 2-D and 3-D TCAD simulations In Tunnel FETs. The interaction between the band-to-band tunnelling, avalanche multiplication, and thermal carrier generation leading to voltage snapback and failure is presented in detail, along with the electro-thermal instability initiated _lamentation. Impact of various technology and device design parameters on the ESD behavior and robustness of TFETs is discussed. The obtained details will be useful in designing ESD protection concepts in future TFET technologies. Experimental ESD studies on Graphene FETs using matured technology platform are carried out to study the impact of diffusive vs. ballistic carrier transport and top-gate vs. back-gate on failure mechanisms. Insights on current saturation in graphene FET in ESD time scales and a novel step by step failure in dielectric capped transistors is presented. Finally, influence of various top-gate designs on the ESD performance is reported. Safe Operating area boundary definitions in Graphene FETs is also explored. Obtained insights on device failures in these budding technologies, will help in building stronger ESD protection concepts in graphene-based technologies.