Development of Synchro-Phasor Algorithms on Parallella - A Credit Card Sized Super Computer

Abstract

In recent years, usage of GPS time-stamped phasor magnitude and angle measure- ments of voltage and current samples, called synchrophasors, is getting great atten- tion for wide area monitoring, protection, and control of large power grids. The University of Berkeley in collaboration with Power Standards Lab has developed a micro-Phasor Measurement Unit (PQUBE) for distribution grids as part of a multi- million dollar ARPA-E funded project, 2013-2016. However, the cost of each micro- PMU device is quite high ( $3500 to develop the device). This thesis focuses on the development of a low-cost PMU. A low cost credit card sized supercomputer open hardware called Parallella has been used in the develop- ment. Parallella contains a dual-core ARM-A9 + FPGA Zynq SoC and Adapteva's epiphany 16-core co-processor linked through FPGA fabric. It consumes less than 5W power. Parallella brings a lot of compute power on a small form factor making it a great choice for academia and industries to experiment with the power of ARM, FPGA, and parallel computing at the edge. Discrete Fourier Transform (DFT) based methods are widely used in commercial PMUs. Spectral leakage is one of the problems associated with DFT implementa- tion during o nominal conditions. Non-integral sampling frequency (due to clock drift) is another problem for DFT based algorithms. However, Phase Locked Loop (PLL) based algorithms are less sensitive to such issues and seem to be a viable op- tion for constrained hardware as their computational and memory requirements are low. In this thesis, di erent PLL-based algorithms are evaluated for synchrophasor application. Double Frequency & Amplitude Compensation Phase Locked Loop (DFAC-PLL) algorithm is found to be more promising for synchrophasor application. Hence, DFAC-PLL has been implemented with pre and post-processing lters on the FPGA of Parallela. A systematic approach for the optimal design of the lters and FPGA implementation on Parallella are proposed in this thesis. DFAC-PLL implementa- tion in simulations as well as on the hardware is tested for compliance with IEEE standard C37.118.1-2018. The total cost, bill of materials (BOM) + CTs + fabrication + assembly cost + taxes, for one unit of the developed PMU is INR 56,800 ( $790). Since only FPGA is used for PMU implementation, ARM and Epiphany can be used for other applications like data analysis, machine learning, etc. which makes Parallella a great edge computing platform for power engineers.