Antiresonance and Noise Suppression Techniques for Digital Power Distribution Networks
Power distribution network (PDN) design was a non-existent entity during the early days of microprocessors due to the low frequency of operation. Once the switching frequencies of the microprocessors started moving towards and beyond MHz regions, the parasitic inductance of the PCB tracks and planes started playing an important role in determining the maximum voltage on a PDN. Voltage regulator module (VRM) sup-plies only the DC power for microprocessors. When the MOSFETs inside a processor switches, it consumes currents during transition time. If this current is not provided, the voltage on the supply rails can go below the specifications of the processor. For lower MHz processors few ceramic-capacitors known as ‘decoupling capacitors’ were connected between power and ground to provide this transient current demand. When the processor frequency increased beyond MHz, the number of capacitors also increased from few numbers to hundreds of them. Nowadays, the PDN is said to be comprising all components from VRM till the die location. It includes VRM, bulk capacitors, PCB power planes, capacitor mounting pads and vias, mount for the electronic package, package capacitors, die mount and internal die capacitance. So, the PDN has evolved into a very complex system over the years. A PDN should provide three distinct roles; 1) provide transient current required by the processor 2) act as a stable reference voltage for processor 3) filter out the noise currents injected by the processor. The first two are required for the correct operation of the processor. Third one is a requirement from analog or other sensitive circuits connected to the same PDN. If the noise exits the printed circuit board (PCB), it can result in conducted and radiated EMI, which can in turn result in failure of a product in EMC testing. Every PDN design starts with the calculation of a target impedance which is given as the ratio of maximum allowed ripple voltage to the maximum transient current required by the processor. The transient current is usually taken as half the average input current. The definition of target impedance assumes that the PDN is flat over the entire frequency of operation, which is true only for a resistive network. This is seldom true for a practical PDN, since it contains inductances and capacitances. Because of this, a practical PDN has an uneven impedance versus frequency envelope. Whenever two capacitors with different self resonant frequencies are connected in parallel, their equivalent impedance produces a pole between the self resonant frequencies known as antiresonance peaks. Because of this, a PDN will have phase angles associated with them. Also, these antiresonance peaks are energy reservoirs which will be excited during the normal operation of a processor by the varying currents. The transient current of a microprocessor is modeled as a gamma function, but for practical cases it can be approximated as triangular waveforms during the transition time which is normally 10% of the time period. Depending upon the micro-operations running inside the processor, the peak value of this waveform varies. This is filtered by the on-chip capacitors, package inductance and package capacitors. Due to power gating, clock gating, IO operations, matrix multiplications and magnetic memory readings the waveforms at the board will be like pulse type, and their widths are determined by these operations. In literatures, these two types of waveforms are used for PDN analysis, depending upon at which point the study is conducted. Chapter 1 introduces the need for PDN design and the main roles of a PDN. The issue of antiresonance is introduced from a PDN perspective. Different types of capacitors used on a PDN are discussed with their strengths and limitations. The general nature of the switching noise injected by a microprocessor is also discussed. This chapter discusses the thesis contributions, and the existing work related to the field. Chapter 2 introduces a new method to calculate the target impedance (Zt ) by including the phase angles of a PDN which is based on a maximum voltage calculation. This new Zt equals to conventional Zt for symmetrical triangular switching current waveforms. The value of new Zt is less than the conventional Zt for trapezoidal excitation patterns. By adding the resonance effects into this, a maximum voltage value is obtained in this chapter. The new method includes the maximum voltage produced on a PDN when multiple antiresonance peaks are present. Example simulations are provided for triangular and pulse type excitations. A measured input current wave-form for PIC16F677 microcontroller driving eight IO ports is provided to prove the assumption of pulse type waveforms. For triangular excitation waveform, the maximum voltage predicted based on the expression was ¡0.6153 V, and the simulated maximum voltage was found to be at ¡0.5412 V which is less than the predicted value. But the predicted value based on Zt method was 1.9845 V. This shows that the conventional as well as the new target impedance method leads to over estimating the maximum voltage in certain cases. This is because most of the harmonics are falling on the minimum impedance values on a PDN. If the PDN envelope is changed by temperature and component tolerances, the maximum voltage can vary. So the best option is to design with the target impedance method. When pulse current excitation was studied for a particular PDN, the maximum voltage produced was -139.39 mV. The target impedance method produced a value of -100.24 mV. The maximum voltage predicted by the equation was -237 mV. So this shows that some times the conventional target impedance method leads to under estimating the PDN voltage. From the studies, it is shown that the time domain analysis is as important as frequency domain analysis. Another important observation is that the antiresonance peaks on a PDN should be damped both in number and peak value. Chapter 3 studies the antiresonance peak suppression methods for general cases. As discussed earlier, the antiresonance peaks are produced when two capacitors with different self resonant frequencies are connected in parallel. This chapter studies the effect of magnetic coupling between the mounting loops of two capacitors in parallel. The mounting loop area contribute to the parasitic inductance of a capacitor, and it is the major contributing factor to it. Other contributing factors are equivalent series inductance (ESL) and plane spreading inductance. The ESL depends on the size and on how the internal plates of the capacitors are formed. The spreading inductance is the inductance contributed by the parts of the planes connecting the capacitor connector vias to the die connections or to other capacitor vias. If the power and ground planes are closer, the spreading inductance is lower. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The inductance contributed by the mounted area of the capacitor is known as mounting inductance. On one/two layer boards dedicated power/ground planes are absent. So the spreading inductance is replaced by PCB track inductances. The dependencies of various circuit parameters on antiresonance peak are studied using circuit theory. A general condition for damping the antiresonance is formulated. The antiresonance peak reduces with Q factor. The conventional critical condition for antiresonance peak damping needs modification when magnetic coupling is present between the mounting loops of two parallel unequal value capacitors. By varying the connection geometry it is possible to obtain negative and positive coupling coefficients. The connection geometries to obtain these two are shown. An example is shown for positive and negative coupling coefficient cases with simulation and experimental results. For the example discussed, RC Æ 32 - for k Æ Å0.6 and RC Æ 64 - for k Æ ¡0.6, where RC is the critical damping value and k is the magnetic coupling coefficient between the two mounting loops. The reason for this is that, the antiresonance peak impedance value is higher for negative coupling coefficient case than that for positive coupling coefficient case. Above the self resonant frequencies of both the capacitors, the equivalent impedance of the parallel capacitors become inductive. This case is studied with two equal value capacitors in parallel. It is shown that the equivalent inductance is lower for negative coupling coefficient case as compared to positive coupling coefficient case. An example is provided with simulation and experimental results. In the experimental results, parasitic inductance is observed to be 2.6 times lower for negative coupling coefficient case than that for positive coupling coefficient case. When equal value capacitors are connected in parallel, it is advantageous to use a negative coupling geometry due to this. Chapter 4 introduces a new method to damp the antiresonance peak using a magnet-ically coupled resistive loop. Reducing the Q factor is an option to suppress the peak. In this new method, the Q factor reduction is achieved by introducing losses by mag-netically coupling a resistive loop. The proposed circuit is analyzed with circuit-theory, and governing equations are obtained. The optimum value of resistance for achieving maximum damping is obtained through analysis. Simulation and experimental results are shown to validate the theory. From the experimental results approximately 247 times reduction in antiresonance peak is observed with the proposed method. Effectiveness of the new method is limited by the magnetic coupling coefficient between the two mounting loops of capacitors. The method can be further improved if the coupling coefficient can be increased at the antiresonance frequency. Chapter 5 focuses on the third objective of a PDN, that is to reduce the noise injected by the microprocessor. A new method is proposed to reduce the conducted noise from a microprocessor with switched super capacitors. The conventional switched capacitor filters are based on the concept that the flying capacitor switching at high frequency looks like a resistor at low frequency. So for using at audio frequencies the flying capacitors were switching at MHz frequencies. In this chapter the opposite of this scenario is studied; the flying capacitors are the energy storage elements of a switched capacitor converter and they switch at lower frequencies as compared to the noise frequencies. Two basic circuits (1:1 voltage conversion ratio) providing noise isolation were discussed. They have distinct steady state input current waveforms and are explained with PSPICE simulations. The inrush current through switches are capable of destroying them in a practical implementation. A practical solution was proposed using PMOS-PNP pair. The self introduced switching noise of the converter is lower when switching frequency is low and turn ON-OFF time is higher. If power metal oxide semiconductor field effect transistor (MOSFET)s are used, the turn ON and turn OFF are slow. The switching frequency can be lowered based on the voltage drop power loss. The governing equations were formulated and simulated. It is found that the switching frequency can be lowered by increasing the capacitance value without affecting the voltage drop and power loss. From the equations, it is found that the design parameters have a cyclic dependency. Noise can short through the parasitic capacitance of the switches. Two circuits were proposed to improve the noise isolation: 1) T switch 2) ¦ switch. Of these, the ¦ switch has the higher measured transfer impedance. Experimental results showed a noise reduction of (40-20) dB for the conducted frequency range of 150 kHz - 30 MHz with the proposed 1:1 switched capacitor converter. One possible improvement of this method is to combine the noise isolation with an existing switched capacitor converter (SCC) topology. The discussed example had a switching frequency of 700 Hz, and it is shown that this can isolate the switching noise in kHz and MHz regions. In a PDN there are antiresonance peaks in kHz regions. If the proposed circuit is kept close to a microprocessor, it can reduce the excitation currents of these low frequency antiresonance peaks. Chapter 6 concludes the thesis by stating the major contributions and applications of the concepts introduced in the thesis. This chapter also discusses the future scope of these concepts.