dc.contributor.advisor | Raghavan, K V | |
dc.contributor.author | Acharya, Aravind N | |
dc.date.accessioned | 2018-04-18T06:46:54Z | |
dc.date.accessioned | 2018-07-31T04:39:04Z | |
dc.date.available | 2018-04-18T06:46:54Z | |
dc.date.available | 2018-07-31T04:39:04Z | |
dc.date.issued | 2018-04-18 | |
dc.date.submitted | 2013 | |
dc.identifier.uri | https://etd.iisc.ac.in/handle/2005/3420 | |
dc.identifier.abstract | http://etd.iisc.ac.in/static/etd/abstracts/4287/G25923-Abs.pdf | en_US |
dc.description.abstract | Model checking is a powerful technique for analyzing reach ability and temporal properties of finite state systems. Model-checking finite state systems has been well-studied and there are well known efficient algorithms for this problem. However these algorithms may not terminate when applied directly to in finite state systems. Counter systems are a class of in fininite state systems where the domain of counter values is possibly in finite. Many practical systems like cache coherence protocols, broadcast protocols etc, can naturally be modeled as counter systems. In this thesis we identify a class of counter systems, and propose a new technique to check whether a system from this class satires’ a given CTL formula. The key novelty of our approach is a way to use existing reach ability analysis techniques to answer both \until" and \global" properties; also our technique for \global" properties is different from previous techniques that work on other classes of counter systems, as well as other classes of in finite state systems. We also provide some results by applying our approach to several natural examples, which illustrates the scope of our approach. | en_US |
dc.language.iso | en_US | en_US |
dc.relation.ispartofseries | G25923 | en_US |
dc.subject | Computer Systems - Testing and Measurement | en_US |
dc.subject | Presburger Counter Systems | en_US |
dc.subject | Presburger Arithmetic | en_US |
dc.subject | Model Checking | en_US |
dc.subject | Presburger Counter Systems - Model Checking | en_US |
dc.subject | Computational Tree Logic (CTL) | en_US |
dc.subject | Generic Algorithms | en_US |
dc.subject | Infinite State Counter Systems - Verification | en_US |
dc.subject | Model Checking Algorithms | en_US |
dc.subject | Counter Systems | en_US |
dc.subject | Acceleration (Counter Systems) | en_US |
dc.subject | Automated Verification | en_US |
dc.subject.classification | Computer Science | en_US |
dc.title | Model-Checking in Presburger Counter Systems using Accelerations | en_US |
dc.type | Thesis | en_US |
dc.degree.name | MSc Engg | en_US |
dc.degree.level | Masters | en_US |
dc.degree.discipline | Faculty of Engineering | en_US |