Browsing Supercomputer Education and Research Centre (SERC) by thesis submitted date"2002"
Now showing items 1-2 of 2
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Extending architectural support for imposing early and local cache coherence in distributed shared-memory multiprocessors
Designing cost-efficient cache coherence protocols has long been pursued in the context of Distributed Shared-memory Multiprocessors (DSM). With increasingly aggressive implementations of DSM systems that use high-performance ... -
Speculative trace scheduling of binary translated code in vliw processors
Very Long Instruction Word (VLIW) processors are well known for their high compute capacity and simple hardware. Because of these properties, these processors are very popular in the embedded processing domain. With the ...