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    Optimizing Matrix Multiplication for the REDEFINE Many-Core Co-processor 

    Kulkarni, Pratik
    Matrix-matrix multiplication is an important operation for many applications and hence it is required to be parallelized optimally for the architecture the applications will run on. REDE- FINE is a many-core co-processor ...

    CDMA Base Station Receive Co-Processor Architecture 

    Santhosam, Charles L (2007-10-23)
    Third generation mobile communication systems promise a greater data rate and new services to the mobile subscribers. 3G systems support up to 2 Mbps of data rate to a fixed subscriber and 144 Kbps of data rate to a fully ...

    Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm 

    Alle, Mythri (2015-07-24)
    Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a ...

    Cooperative Execution of Opencl Programs on Multiple Heterogeneous Devices 

    Pandit, Prasanna Vasant (2018-05-01)
    Computing systems have become heterogeneous with the increasing prevalence of multi-core CPUs, Graphics Processing Units (GPU) and other accelerators in them. OpenCL has emerged as an attractive programming framework for ...

    Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture 

    Biswas, Prasenjit (2013-07-10)
    Application domains such as Bio-informatics, DSP, Structural Biology, Fluid Dynamics, high resolution direction finding, state estimation, adaptive noise cancellation etc. demand high performance computing solutions for ...

    Adaptive Grid Meta Scheduling - A QoS Perspective 

    Nainwal, Kalash Chandra (2011-09-06)

    RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture 

    Satrawala, Amar Nath (2011-01-20)
    REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation ...

    Cache Coherence State Based Replacement Policies 

    Agarwal, Tanuj Kumar (2018-07-14)
    Cache replacement policies can play a pivotal role in the overall performance of a system by preserving data locality and thus limiting the o -chip accesses. In a shared memory system, a cache coherence protocol is necessary ...

    Architecting Resource Management Services For Computational Grids : Patterns And Performance Models 

    Prem, Hema (2011-09-13)

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    AuthorAgarwal, Tanuj Kumar (1)Alle, Mythri (1)Biswas, Prasenjit (1)Kulkarni, Pratik (1)Nainwal, Kalash Chandra (1)Pandit, Prasanna Vasant (1)Prem, Hema (1)Santhosam, Charles L (1)Satrawala, Amar Nath (1)Subject
    Computer Architecture (9)
    Computer Science (6)Grid Computing (2)Adaptive Grid Meta Scheduling (1)Base Stations (1)Cache Coherence (1)Cache Coherence Protocol (1)Cache Memory (1)Cache Replacement Policies (1)Cache Replacement Policy (1)... View MoreDate Issued2010 - 2018 (7)2007 - 2009 (1)Has File(s)Yes (9)

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