Browsing Division of Interdisciplinary Research by Advisor "Nandy, S K"
Now showing items 1-20 of 30
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Accelerated and Accurate Alignment of Short Reads in High Throughput Next Generation Sequencing [NGS] Platforms
The genome of an organism encompasses the unique set of genetic instructions for every individual in a species. The genome, in totality, guides the course of evolution, development, genetic and epigenetic growth factors ... -
An Accelerator for Machine Learning Based Classifiers
Artificial Neural Networks (ANNs) are algorithmic techniques that simulate biological neural systems. Typical realization of ANNs are software solutions using High Level Languages (HLLs) such as C, C++, etc. Such solutions ... -
Adaptive Grid Meta Scheduling - A QoS Perspective
(2011-09-06) -
ASIC Implementation of A High Throughput, Low Latency, Memory Optimized FFT Processor
(2016-09-09)The rapid advancements in semiconductor technology have led to constant shrinking of transistor sizes as per Moore's Law. Wireless communications is one field which has seen explosive growth, thanks to the cramming of more ... -
CDMA Base Station Receive Co-Processor Architecture
(2007-10-23)Third generation mobile communication systems promise a greater data rate and new services to the mobile subscribers. 3G systems support up to 2 Mbps of data rate to a fixed subscriber and 144 Kbps of data rate to a fully ... -
A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution
(2014-04-23)A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units (viz. Function Units (FUs), Arithmetic Logic Units (ALUs)). These units ... -
Compiler controlled Task Management in Runtime Systems for Dynamic Data ow Model of Execution
For the past 40 years, relentless focus on Moore's Law transistor scaling has provided ever-increasing transistor performance and density. An ever increasing demand for large scale parallelism has driven hardware designers ... -
Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm
(2015-07-24)Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a ... -
Complexity effective ASIP architectures for network processing and multimedia acceleration
Advancements in VLSI technology have significantly improved microprocessor performance over the past decades. However, contemporary general-purpose processors fall short in meeting the demands of emerging application ... -
Data-Driven Approach to Estimate WCET for Real-Time Systems
Estimating Worst-Case Execution Time (WCET) is paramount for developing Real-Time and Em- bedded systems. The operating system’s scheduler uses the estimated WCET to schedule each task of these systems before the assigned ... -
Early Detection Of Artificial Deadlocks In Process Networks
(2011-09-07) -
Elasticity in IaaS Cloud, Preserving Performance SLAs
(2017-11-14)Infrastructure-as-a-Service(IaaS), one of the service models of cloud computing, provides resources in the form of Virtual Machines(VMs). Many applications hosted on the IaaS cloud have time varying workloads. These kind ... -
Energy Efficient Flexible Baseband Processing for Mobile and Cognitive Radios
Wireless communication has become an integral part of human life, and one of the dominating applications in today’s world. Mobile communication devices are the largest consumer electronic group in terms of volume. In 2007, ... -
Extending architectural support for imposing early and local cache coherence in distributed shared-memory multiprocessors
Designing cost-efficient cache coherence protocols has long been pursued in the context of Distributed Shared-memory Multiprocessors (DSM). With increasingly aggressive implementations of DSM systems that use high-performance ... -
Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture
(2013-07-10)Application domains such as Bio-informatics, DSP, Structural Biology, Fluid Dynamics, high resolution direction finding, state estimation, adaptive noise cancellation etc. demand high performance computing solutions for ... -
Hardware-Software Co-Design Accelerators for Sparse BLAS
Sparse Basic Linear Algebra Subroutines (Sparse BLAS) is an important library. Sparse BLAS includes three levels of subroutines. Level 1, Level2 and Level 3 Sparse BLAS routines. Level 1 Sparse BLAS routines do computations ... -
A Novel Algorithm-Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification
In EDA industry, design-under-test (DUT) is a pre-silicon digital design which is still undergoing testing phase. We perform functional-verification of a DUT to verify whether the DUT conforms to the specifications. Functional ... -
Novel Neural Architectures based on Recurrent Connections and Symmetric Filters for Visual Processing
Artificial Neural Networks (ANN) have been very successful due to their ability to extract meaningful information without any need for pre-processing raw data. First artificial neural networks were created in essence to ... -
On the effectiveness of exploiting instruction level reuse in superscalar microprocessor : Power-performance prespective
Modern microprocessors exploit Instruction Level Parallelism (ILP) by employing substantial on-chip resources and incorporating microarchitectural features that exploit properties of programs. Among program attributes, ...