Now showing items 1-3 of 3

    • Instruction scheduling for RISC processors 

      Venugopal, R
      Instruction scheduling is the process of reordering instructions (whether assembly code or code in some other form) so as to make fuller use of the resources provided by the processor. In the case of RISC processors, ...
    • Integrated Scheduling For Clustered VLIW Processors 

      Nagpal, Rahul (Indian Institute of Science, 2005-11-25)
      Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Scheduling for clustered architectures ...
    • Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques 

      Nagarakatte, Santosh G (2009-05-19)
      Instruction scheduling and Software pipelining are important compilation techniques which reorder instructions in a program to exploit instruction level parallelism. They are essential for enhancing instruction level ...